From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 103703 invoked by alias); 25 Apr 2017 08:25:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 102278 invoked by uid 89); 25 Apr 2017 08:25:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=D*cavium.com, submission, pinski, deals X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 25 Apr 2017 08:25:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 46A1815A2; Tue, 25 Apr 2017 01:25:42 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3D9E83F3E1; Tue, 25 Apr 2017 01:25:41 -0700 (PDT) Message-ID: <58FF0803.5070007@foss.arm.com> Date: Tue, 25 Apr 2017 08:37:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Hurugalawadi, Naveen" , "gcc-patches@gcc.gnu.org" CC: "Pinski, Andrew" , James Greenhalgh , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2017-04/txt/msg01109.txt.bz2 Hi Naveen, On 09/12/16 07:02, Hurugalawadi, Naveen wrote: > Hi, > > Sorry. Missed out the testcase in patch submission. > Added the missing testcase along with the ChangeLog. > Please review the same and let us know if thats okay? It would be useful if you expanded a bit on the approach used to generate the improved codegen, or at least show for the testcase what code was generated before this patch and what is generated after this patch. > 2016-12-09 Andrew PInski > > gcc > * config/aarch64/aarch64.c (aarch64_expand_vector_init): > Improve vector initialization code gen. > gcc/testsuite > * gcc.target/aarch64/pr71663.c: New Testcase. + /* If there is only varables, try to optimize + the inseration using dup for the most common element + followed by insertations. */ Some typos: s/is only varables/are only variable elements/, s/inseration/insertion/, s/insertations/insertions/. + if (n_var == n_elts && n_elts <= 16) diff --git a/gcc/testsuite/gcc.target/aarch64/pr71663.c b/gcc/testsuite/gcc.target/aarch64/pr71663.c new file mode 100644 index 0000000..c8df847 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr71663.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float c, float d) +{ + return (vector float) { a, b, c, d }; +} A large part of the aarch64.c hunk of your patch deals with finding the most commonly-occuring element in the vector of variables, yet in your testcase all variables appear exactly once. Perhaps worth adding a testcase where one of the vector elements appears more than the others? I'd guess the codegen then would be better with this patch? Cheers, Kyrill