From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 62330 invoked by alias); 25 Apr 2017 15:43:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 61073 invoked by uid 89); 25 Apr 2017 15:43:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=bank X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 25 Apr 2017 15:43:27 +0000 Received: from svr-orw-mbx-03.mgc.mentorg.com ([147.34.90.203]) by relay1.mentorg.com with esmtp id 1d32ci-00016o-2f from Sandra_Loosemore@mentor.com ; Tue, 25 Apr 2017 08:43:28 -0700 Received: from [127.0.0.1] (147.34.91.1) by svr-orw-mbx-03.mgc.mentorg.com (147.34.90.203) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 25 Apr 2017 08:43:24 -0700 Subject: Re: [PATCH 2/3] [ARC] Fast interrupts support. To: Claudiu Zissulescu , References: <1493125424-7298-1-git-send-email-claziss@synopsys.com> <1493125424-7298-3-git-send-email-claziss@synopsys.com> CC: , From: Sandra Loosemore Message-ID: <58FF6E9B.6080205@codesourcery.com> Date: Tue, 25 Apr 2017 15:54:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1493125424-7298-3-git-send-email-claziss@synopsys.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: svr-orw-mbx-02.mgc.mentorg.com (147.34.90.202) To svr-orw-mbx-03.mgc.mentorg.com (147.34.90.203) X-SW-Source: 2017-04/txt/msg01222.txt.bz2 On 04/25/2017 07:03 AM, Claudiu Zissulescu wrote: > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index cebafe6..aa5cd27 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -606,7 +606,8 @@ Objective-C and Objective-C++ Dialects}. > -mnorm -mspfp -mspfp-compact -mspfp-fast -msimd -msoft-float -mswap @gol > -mcrc -mdsp-packa -mdvbf -mlock -mmac-d16 -mmac-24 -mrtsc -mswape @gol > -mtelephony -mxy -misize -mannotate-align -marclinux -marclinux_prof @gol > --mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved @gol > +-mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved > +-mrgf-banked-regs @gol Please don't remove @gol at the end of the line. It's easier to maintain these option lists in the docs if the line breaks in the source reflect where they're being inserted in the output. > -mvolatile-cache -mtp-regno=@var{regno} @gol > -malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc @gol > -mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol > @@ -14587,6 +14588,18 @@ A register range always starts with r0. Registers blink and lp_count > can be specified individually. Only valid for ARC EM and ARC HS > cores. > > +@item -mrgf-banked-regs="NUMBER" Please use @var markup here. Don't use quotes unless they're a literal part of the syntax. > +@opindex mrgf-banked-regs > +Specifies the number of registers replicated in second register bank > +on entry to fast interrupt. Fast interrupts are interrupts with the > +highest priority level P0. These interrupts save only PC and STATUS32 > +registers to avoid memory transactions during interrupt entry and exit > +sequences. Use this option when you are using fast interrupts in an > +ARC V2 family processor. > + > +Permitted values are 4, 8, 16, 32 and specify the number of registers > +that are covered by the second register bank. > + > @end table > > The following options are passed through to the assembler, and also -Sandra