From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 55806 invoked by alias); 1 Jun 2017 14:02:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 55794 invoked by uid 89); 1 Jun 2017 14:02:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Jun 2017 14:02:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB62B1596; Thu, 1 Jun 2017 07:02:03 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 196A63F58B; Thu, 1 Jun 2017 07:02:02 -0700 (PDT) Message-ID: <59301E59.5080404@foss.arm.com> Date: Thu, 01 Jun 2017 14:02:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: Re: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns References: <58B56D3E.3090704@foss.arm.com> <58FDC775.4080003@foss.arm.com> <59104F9E.4060700@foss.arm.com> In-Reply-To: <59104F9E.4060700@foss.arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2017-06/txt/msg00041.txt.bz2 Ping. Thanks, Kyrill On 08/05/17 11:59, Kyrill Tkachov wrote: > Ping. > > Thanks, > Kyrill > > On 24/04/17 10:37, Kyrill Tkachov wrote: >> Pinging this back into context so that I don't forget about it... >> >> https://gcc.gnu.org/ml/gcc-patches/2017-02/msg01648.html >> >> Thanks, >> Kyrill >> >> On 28/02/17 12:29, Kyrill Tkachov wrote: >>> Hi all, >>> >>> For the testcase in this patch we currently generate: >>> foo: >>> mov w1, 0 >>> ldaxr w2, [x0] >>> cmp w2, 3 >>> bne .L2 >>> stxr w3, w1, [x0] >>> cmp w3, 0 >>> .L2: >>> cset w0, eq >>> ret >>> >>> Note that the STXR could have been storing the WZR register instead of moving zero into w1. >>> This is due to overly strict predicates and constraints in the store exclusive pattern and the >>> atomic compare exchange expanders and splitters. >>> This simple patch fixes that in the patterns concerned and with it we can generate: >>> foo: >>> ldaxr w1, [x0] >>> cmp w1, 3 >>> bne .L2 >>> stxr w2, wzr, [x0] >>> cmp w2, 0 >>> .L2: >>> cset w0, eq >>> ret >>> >>> >>> Bootstrapped and tested on aarch64-none-linux-gnu. >>> Ok for GCC 8? >>> >>> Thanks, >>> Kyrill >>> >>> 2017-02-28 Kyrylo Tkachov >>> >>> * config/aarch64/atomics.md (atomic_compare_and_swap expander): >>> Use aarch64_reg_or_zero predicate for operand 4. >>> (aarch64_compare_and_swap define_insn_and_split): >>> Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint. >>> (aarch64_store_exclusive): Likewise for operand 2. >>> >>> 2017-02-28 Kyrylo Tkachov >>> >>> * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test. >> >