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Date: Fri, 02 Jun 2017 10:39:00 -0000
From: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
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To: GCC Patches <gcc-patches@gcc.gnu.org>
CC: Marcus Shawcroft <marcus.shawcroft@arm.com>,  Richard Earnshaw <Richard.Earnshaw@arm.com>, James Greenhalgh <james.greenhalgh@arm.com>
Subject: Re: [PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern
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Ping.

Thanks,
Kyrill

On 11/05/17 11:15, Kyrill Tkachov wrote:
> Ping.
>
> https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00933.html
>
> Thanks,
> Kyrill
>
> On 21/04/17 09:34, Kyrill Tkachov wrote:
>> Hi all,
>>
>> For the testcase in the patch we currently miss a combination and generate:
>> foo:
>>         dup     h1, v1.h[2]
>>         ins     v0.h[3], v1.h[0]
>>         ret
>>
>> bar:
>>         dup     h1, v1.h[2]
>>         ins     v0.h[3], v1.h[0]
>>         ret
>>
>> This is because the *aarch64_simd_vec_copy_lane<mode> pattern is not defined
>> for HF vector modes. I think that's just a simple oversight fixed by using
>> the VALL_F16 mode iterator instead of VALL (it just adds V4HF and V8HF on top of VALL)
>> and we can use the proper INS pattern and generate:
>> foo:
>>         ins     v0.h[3], v1.h[2]
>>         ret
>>
>> bar:
>>         ins     v0.h[3], v1.h[2]
>>         ret
>>
>> Bootstrapped and tested on aarch64-none-linux-gnu.
>> Ok for GCC 8?
>>
>> Thanks,
>> Kyrill
>>
>> 2017-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>     * config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
>>     Use VALL_F16 iterator rather than VALL.
>>
>> 2017-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>     * gcc.target/aarch64/hfmode_ins_1.c: New test.
>>
>