commit f8725ffd1375a8347cc8f4f183262c08ce2f73c6
Author: Renlin Li <renlin.li@arm.com>
Date:   Tue May 23 16:46:31 2017 +0100

    [AARCH64]Add 'r' integer operand modifier. Document the be extend asm modifier
    for aarch64 target.
    
    gcc/ChangeLog:
    
    	PR target/63359
    	* config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' modifier.
    	* doc/extend.texi (AArch64Operandmodifiers): New section.
    
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5707e53..d1c400f 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -5132,6 +5132,26 @@ aarch64_print_operand (FILE *f, rtx x, int code)
       asm_fprintf (f, "0x%wx", UINTVAL (x) & 0xffff);
       break;
 
+    case 'r':
+	{
+	  machine_mode mode = GET_MODE (x);
+	  switch (mode)
+	    {
+	    case QImode:
+	    case HImode:
+	    case SImode:
+	      code = 'w';
+	      break;
+	    case DImode:
+	      code = 'x';
+	      break;
+	    default:
+	      output_operand_lossage
+		("invalid operand mode for register modifier 'r'");
+	    }
+	}
+      /* Fall through.  */
+
     case 'w':
     case 'x':
       /* Print a general register name or the zero register (32-bit or
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 60a1a3f..d1c830d 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -8264,7 +8264,9 @@ is undefined if @var{a} is modified before using @var{b}.
 @code{asm} supports operand modifiers on operands (for example @samp{%k2} 
 instead of simply @samp{%2}). Typically these qualifiers are hardware 
 dependent. The list of supported modifiers for x86 is found at 
-@ref{x86Operandmodifiers,x86 Operand modifiers}.
+@ref{x86Operandmodifiers,x86 Operand modifiers}.  The list of supported
+modifiers for AArch64 is found at
+@ref{AArch64Operandmodifiers,AArch64 Operand modifiers}.
 
 If the C code that follows the @code{asm} makes no use of any of the output 
 operands, use @code{volatile} for the @code{asm} statement to prevent the 
@@ -8491,7 +8493,9 @@ optimizers may discard the @code{asm} statement as unneeded
 @code{asm} supports operand modifiers on operands (for example @samp{%k2} 
 instead of simply @samp{%2}). Typically these qualifiers are hardware 
 dependent. The list of supported modifiers for x86 is found at 
-@ref{x86Operandmodifiers,x86 Operand modifiers}.
+@ref{x86Operandmodifiers,x86 Operand modifiers}.  The list of supported
+modifiers for AArch64 is found at
+@ref{AArch64Operandmodifiers,AArch64 Operand modifiers}.
 
 In this example using the fictitious @code{combine} instruction, the 
 constraint @code{"0"} for input operand 1 says that it must occupy the same 
@@ -8659,6 +8663,70 @@ error:
 @}
 @end example
 
+@anchor{AArch64Operandmodifiers}
+@subsubsection AArch64 Operand Modifiers
+References to input, output, and goto operands in the assembler template
+of extended @code{asm} statements can use
+modifiers to affect the way the operands are formatted in
+the code output to the assembler.
+
+The table blow descirbes the list of useful register operand modifiers which
+might be used in extended @code{asm}. It is not necessary a complete list
+of modifiers supported by the AArch64 backend.
+
+@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand}
+@headitem Modifier @tab Description @tab Operand
+@item @code{r}
+@tab Print the opcode suffix for the size of the current integer operand (one of @code{w}/@code{x}).
+@tab @code{%r0}
+@item @code{w}
+@tab Print the SImode name of the register.
+@tab @code{%w0}
+@item @code{x}
+@tab Print the DImode name of the register.
+@tab @code{%x0}
+@item @code{h}
+@tab Print the HFmode name of the register.
+@tab @code{%h0}
+@item @code{s}
+@tab Print the SFmode name of the register.
+@tab @code{%s0}
+@item @code{d}
+@tab Print the DFmode name of the register.
+@tab @code{%d0}
+@item @code{q}
+@tab Print the TFmode name of the register.
+@tab @code{%q0}
+@end multitable
+
+Without specifying any modifiers to a register operand, the default @code{x}
+register name is used for integer operand, @code{v} register name is used for
+floating pointer operand. For example:
+
+@example
+int load_int (int *ptr, int offset)
+@{
+  int  result;
+  asm ("ldr %0, [%1, %2]\n\t"
+       : "=r" (result)
+       : "r" (ptr), "r"(offset));
+  return result;
+@}
+@end example
+
+The following code will be generated:
+
+@smallexample
+ldr x0, [x0, x1]
+@end smallexample
+
+If proper modifier is used for the first operand @code{result}, say @code{w} or
+@code{r}, it will generate the following code as one would expected:
+
+@smallexample
+ldr w0, [x0, x1]
+@end smallexample
+
 @anchor{x86Operandmodifiers}
 @subsubsection x86 Operand Modifiers