From: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
To: James Greenhalgh <james.greenhalgh@arm.com>, gcc-patches@gcc.gnu.org
Cc: nd@arm.com, richard.earnshaw@arm.com, marcus.shawcroft@arm.com
Subject: Re: [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size
Date: Mon, 12 Jun 2017 14:28:00 -0000 [thread overview]
Message-ID: <593EA524.50805@foss.arm.com> (raw)
In-Reply-To: <1497275640-6630-1-git-send-email-james.greenhalgh@arm.com>
On 12/06/17 14:53, James Greenhalgh wrote:
> Hi,
>
> In the AArch64 backend and scheduling models there is some confusion as to
> what the load1/load2 etc. scheduling types refer to. This leads to us using
> load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit
> loads in AArch32 and 128-bit loads in AArch64. That leads to an undesirable
> confusion in scheduling.
>
> Fixing it is easy, but mechanical and boring. Essentially,
>
> s/load1/load_4/
> s/load2/load_8/
> s/load3/load_12/
> s/load4/load_16/
> s/store1/store_4/
> s/store2/store_8/
> s/store3/store_12/
> s/store4/store_16/
So the number now is the number of bytes being loaded?
> Across all sorts of pipeline models, and the two backends.
>
> I have intentionally not modified any of the patterns which now look obviously
> incorrect. I'll be doing a second pass over the AArch64 back-end in patch
> 2/2 which will fix these bugs. The AArch32 back-end looked to me to get this
> correct.
>
> Bootstrapped on AArch64 and ARM without issue - there's no functional
> change here.
>
> OK?
Ok from an arm perspective.
Kyrill
>
> Thanks,
> James
>
> ---
> gcc/
>
> 2017-06-12 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16
> and store1/2/3/4 to store_4/8/12/16.
> * config/aarch64/aarch64.md: Update for rename.
> * config/arm/arm.md: Likewise.: Likewise.
> * config/arm/arm.c: Likewise.
> * config/arm/thumb1.md: Likewise.
> * config/arm/thumb2.md: Likewise.
> * config/arm/vfp.md: Likewise.
> * config/arm/arm-generic.md: Likewise.
> * config/arm/arm1020e.md: Likewise.
> * config/arm/arm1026ejs.md: Likewise.
> * config/arm/arm1136jfs.md: Likewise.
> * config/arm/arm926ejs.md: Likewise.
> * config/arm/cortex-a15.md: Likewise.
> * config/arm/cortex-a17.md: Likewise.
> * config/arm/cortex-a5.md: Likewise.
> * config/arm/cortex-a53.md: Likewise.
> * config/arm/cortex-a57.md: Likewise.
> * config/arm/cortex-a7.md: Likewise.
> * config/arm/cortex-a8.md: Likewise.
> * config/arm/cortex-a9.md: Likewise.
> * config/arm/cortex-m4.md: Likewise.
> * config/arm/cortex-m7.md: Likewise.
> * config/arm/cortex-r4.md: Likewise.
> * config/arm/exynos-m1.md: Likewise.
> * config/arm/fa526.md: Likewise.
> * config/arm/fa606te.md: Likewise.
> * config/arm/fa626te.md: Likewise.
> * config/arm/fa726te.md: Likewise.
> * config/arm/fmp626.md: Likewise.
> * config/arm/iwmmxt.md: Likewise.
> * config/arm/ldmstm.md: Likewise.
> * config/arm/marvell-pj4.md: Likewise.
> * config/arm/xgene1.md: Likewise.
> * config/aarch64/thunderx.md: Likewise.
> * config/aarch64/thunderx2t99.md: Likewise.
>
next prev parent reply other threads:[~2017-06-12 14:28 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-12 13:54 James Greenhalgh
2017-06-12 13:54 ` [Patch AArch64 2/2] Fix memory sizes to load/store patterns James Greenhalgh
2017-06-21 10:50 ` James Greenhalgh
2017-07-03 10:47 ` James Greenhalgh
2017-07-03 10:47 ` James Greenhalgh
2017-07-27 18:10 ` James Greenhalgh
2017-09-12 15:00 ` James Greenhalgh
2017-06-12 14:28 ` Kyrill Tkachov [this message]
2017-06-21 10:50 ` [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size James Greenhalgh
2017-07-27 18:09 ` James Greenhalgh
2017-09-12 14:54 James Greenhalgh
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