From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 37660 invoked by alias); 12 Jun 2017 14:28:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 36133 invoked by uid 89); 12 Jun 2017 14:28:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.9 required=5.0 tests=BAYES_00,GIT_PATCH_2,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 12 Jun 2017 14:28:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25D981596; Mon, 12 Jun 2017 07:28:55 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39C313F557; Mon, 12 Jun 2017 07:28:54 -0700 (PDT) Message-ID: <593EA524.50805@foss.arm.com> Date: Mon, 12 Jun 2017 14:28:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: James Greenhalgh , gcc-patches@gcc.gnu.org CC: nd@arm.com, richard.earnshaw@arm.com, marcus.shawcroft@arm.com Subject: Re: [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size References: <1497275640-6630-1-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1497275640-6630-1-git-send-email-james.greenhalgh@arm.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2017-06/txt/msg00801.txt.bz2 On 12/06/17 14:53, James Greenhalgh wrote: > Hi, > > In the AArch64 backend and scheduling models there is some confusion as to > what the load1/load2 etc. scheduling types refer to. This leads to us using > load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit > loads in AArch32 and 128-bit loads in AArch64. That leads to an undesirable > confusion in scheduling. > > Fixing it is easy, but mechanical and boring. Essentially, > > s/load1/load_4/ > s/load2/load_8/ > s/load3/load_12/ > s/load4/load_16/ > s/store1/store_4/ > s/store2/store_8/ > s/store3/store_12/ > s/store4/store_16/ So the number now is the number of bytes being loaded? > Across all sorts of pipeline models, and the two backends. > > I have intentionally not modified any of the patterns which now look obviously > incorrect. I'll be doing a second pass over the AArch64 back-end in patch > 2/2 which will fix these bugs. The AArch32 back-end looked to me to get this > correct. > > Bootstrapped on AArch64 and ARM without issue - there's no functional > change here. > > OK? Ok from an arm perspective. Kyrill > > Thanks, > James > > --- > gcc/ > > 2017-06-12 James Greenhalgh > > * config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16 > and store1/2/3/4 to store_4/8/12/16. > * config/aarch64/aarch64.md: Update for rename. > * config/arm/arm.md: Likewise.: Likewise. > * config/arm/arm.c: Likewise. > * config/arm/thumb1.md: Likewise. > * config/arm/thumb2.md: Likewise. > * config/arm/vfp.md: Likewise. > * config/arm/arm-generic.md: Likewise. > * config/arm/arm1020e.md: Likewise. > * config/arm/arm1026ejs.md: Likewise. > * config/arm/arm1136jfs.md: Likewise. > * config/arm/arm926ejs.md: Likewise. > * config/arm/cortex-a15.md: Likewise. > * config/arm/cortex-a17.md: Likewise. > * config/arm/cortex-a5.md: Likewise. > * config/arm/cortex-a53.md: Likewise. > * config/arm/cortex-a57.md: Likewise. > * config/arm/cortex-a7.md: Likewise. > * config/arm/cortex-a8.md: Likewise. > * config/arm/cortex-a9.md: Likewise. > * config/arm/cortex-m4.md: Likewise. > * config/arm/cortex-m7.md: Likewise. > * config/arm/cortex-r4.md: Likewise. > * config/arm/exynos-m1.md: Likewise. > * config/arm/fa526.md: Likewise. > * config/arm/fa606te.md: Likewise. > * config/arm/fa626te.md: Likewise. > * config/arm/fa726te.md: Likewise. > * config/arm/fmp626.md: Likewise. > * config/arm/iwmmxt.md: Likewise. > * config/arm/ldmstm.md: Likewise. > * config/arm/marvell-pj4.md: Likewise. > * config/arm/xgene1.md: Likewise. > * config/aarch64/thunderx.md: Likewise. > * config/aarch64/thunderx2t99.md: Likewise. >