From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 86447 invoked by alias); 20 Jun 2017 08:30:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 86352 invoked by uid 89); 20 Jun 2017 08:30:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Jun 2017 08:30:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E83A2344; Tue, 20 Jun 2017 01:30:41 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 92DE73F41F; Tue, 20 Jun 2017 01:30:40 -0700 (PDT) Message-ID: <5948DD2E.30107@foss.arm.com> Date: Tue, 20 Jun 2017 08:30:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Andrew Pinski CC: GCC Patches , Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: Re: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns References: <58B56D3E.3090704@foss.arm.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2017-06/txt/msg01405.txt.bz2 Hi Andrew, On 20/06/17 06:06, Andrew Pinski wrote: > On Tue, Feb 28, 2017 at 4:29 AM, Kyrill Tkachov > wrote: >> Hi all, >> >> For the testcase in this patch we currently generate: >> foo: >> mov w1, 0 >> ldaxr w2, [x0] >> cmp w2, 3 >> bne .L2 >> stxr w3, w1, [x0] >> cmp w3, 0 >> .L2: >> cset w0, eq >> ret >> >> Note that the STXR could have been storing the WZR register instead of >> moving zero into w1. >> This is due to overly strict predicates and constraints in the store >> exclusive pattern and the >> atomic compare exchange expanders and splitters. >> This simple patch fixes that in the patterns concerned and with it we can >> generate: >> foo: >> ldaxr w1, [x0] >> cmp w1, 3 >> bne .L2 >> stxr w2, wzr, [x0] >> cmp w2, 0 >> .L2: >> cset w0, eq >> ret >> >> >> Bootstrapped and tested on aarch64-none-linux-gnu. >> Ok for GCC 8? > > This patch broke compiling with -march=+lse > > ./home/apinski/src/local5/gcc/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c:9:1: > error: unrecognizable insn: > } > ^ > (insn 6 3 7 2 (parallel [ > (set (reg:CC 66 cc) > (unspec_volatile:CC [ > (const_int 0 [0]) > ] UNSPECV_ATOMIC_CMPSW)) > (set (reg:SI 78) > (mem/v:SI (reg/v/f:DI 77 [ a ]) [-1 S4 A32])) > (set (mem/v:SI (reg/v/f:DI 77 [ a ]) [-1 S4 A32]) > (unspec_volatile:SI [ > (const_int 3 [0x3]) > (const_int 0 [0]) > (const_int 1 [0x1]) > (const_int 2 [0x2]) > (const_int 2 [0x2]) > ] UNSPECV_ATOMIC_CMPSW)) > ]) "/home/apinski/src/local5/gcc/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c":8 > -1 > (nil)) > during RTL pass: vregs > > Note also your new testcase is broken even for defaulting to +lse as > it is not going to match stxr. I might be the only person who tests > +lse by default :). I reproduced the ICE, sorry for the trouble. I believe the fix is as simple as relaxing the register_operand predicate on the "value" operand of the LSE cas* patterns to aarch64_reg_or_zero (and extending the constraint as well). This fixes the ICE for me. I'll test a patch and submit ASAP. Kyrill > Thanks, > Andrew Pinski > >> Thanks, >> Kyrill >> >> 2017-02-28 Kyrylo Tkachov >> >> * config/aarch64/atomics.md (atomic_compare_and_swap expander): >> Use aarch64_reg_or_zero predicate for operand 4. >> (aarch64_compare_and_swap define_insn_and_split): >> Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint. >> (aarch64_store_exclusive): Likewise for operand 2. >> >> 2017-02-28 Kyrylo Tkachov >> >> * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test.