From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 106657 invoked by alias); 27 Jun 2017 15:28:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 106458 invoked by uid 89); 27 Jun 2017 15:28:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=renlin, meet X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Jun 2017 15:28:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A94D344; Tue, 27 Jun 2017 08:27:59 -0700 (PDT) Received: from [10.2.207.43] (e104453-lin.cambridge.arm.com [10.2.207.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 948423F41F; Tue, 27 Jun 2017 08:27:58 -0700 (PDT) Subject: Re: [RFC][AARCH64]Add 'r' integer register operand modifier. Document the common asm modifier for aarch64 target. To: Andrew Pinski References: <59368A74.2060908@foss.arm.com> Cc: "gcc-patches@gcc.gnu.org" , James Greenhalgh , Ramana Radhakrishnan , Richard Earnshaw From: Renlin Li Message-ID: <59527975.1060304@foss.arm.com> Date: Tue, 27 Jun 2017 15:28:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg02049.txt.bz2 Hi Andrew, On 25/06/17 22:38, Andrew Pinski wrote: > On Tue, Jun 6, 2017 at 3:56 AM, Renlin Li wrote: >> Hi all, >> >> In this patch, a new integer register operand modifier 'r' is added. This >> will use the >> proper register name according to the mode of corresponding operand. >> >> 'w' register for scalar integer mode smaller than DImode >> 'x' register for DImode >> >> This allows more flexibility and would meet people's expectations. >> It will help for ILP32 and LP64, and big-endian case. >> >> A new section is added to document the AArch64 operand modifiers which might >> be used in inline assembly. It's not an exhaustive list covers every >> modifier. >> Only the most common and useful ones are documented. >> >> The default behavior of integer operand without modifier is clearly >> documented >> as well. It's not changed so that the patch shouldn't break anything. >> >> So with this patch, it should resolve the issues in PR63359. >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 >> >> >> aarch64-none-elf regression test Okay. Okay to check in? > > I think 'r' modifier is very fragile and can be used incorrectly and > wrong in some cases really.. The user could always (or be encouraged to) opt to a strict register modifier to enforce consistent behavior in all cases. I agree the flexibility might bring unexpected behavior in corner cases. Do you have any examples to share off the top of your head? So that we can discuss the benefit and pitfalls, and decide to improve the patch or withdraw it. > I like the documentation though. Thanks, Renlin > > Thanks, > Andrew > >> >> gcc/ChangeLog: >> >> 2017-06-06 Renlin Li >> >> PR target/63359 >> * config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' >> modifier. >> * doc/extend.texi (AArch64Operandmodifiers): New section.