* [PATCH] LoongArch: Use iorn and andn standard pattern names.
@ 2024-07-27 8:54 Lulu Cheng
2024-07-27 19:30 ` Andrew Pinski
0 siblings, 1 reply; 3+ messages in thread
From: Lulu Cheng @ 2024-07-27 8:54 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu
gcc/ChangeLog:
* config/loongarch/lasx.md (xvandn<mode>3): Rename to ...
(andn<mode>3): This.
(xvorn<mode>3): Rename to ...
(iorn<mode>3): This.
* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v):
Defined as the modified name.
(CODE_FOR_lsx_vorn_v): Likewise.
(CODE_FOR_lasx_xvandn_v): Likewise.
(CODE_FOR_lasx_xvorn_v): Likewise.
* config/loongarch/loongarch.md (<optab>n<mode>): Rename to ...
(<optab>n<mode>3): This.
* config/loongarch/lsx.md (vandn<mode>3): Rename to ...
(andn<mode>3): This.
(vorn<mode>3): Rename to ...
(iorn<mode>3): This.
---
gcc/config/loongarch/lasx.md | 4 ++--
gcc/config/loongarch/loongarch-builtins.cc | 8 ++++----
gcc/config/loongarch/loongarch.md | 2 +-
gcc/config/loongarch/lsx.md | 4 ++--
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 7bd61f8ed5b..c5fe04de86c 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -2716,7 +2716,7 @@ (define_insn "lasx_vext2xv_d<u>_b<u>"
(set_attr "mode" "V4DI")])
;; Extend loongson-sx to loongson-asx.
-(define_insn "xvandn<mode>3"
+(define_insn "andn<mode>3"
[(set (match_operand:LASX 0 "register_operand" "=f")
(and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f"))
(match_operand:LASX 2 "register_operand" "f")))]
@@ -4637,7 +4637,7 @@ (define_insn "lasx_xvssrlrn_<hlasxfmt>_<lasxfmt>"
[(set_attr "type" "simd_int_arith")
(set_attr "mode" "<MODE>")])
-(define_insn "xvorn<mode>3"
+(define_insn "iorn<mode>3"
[(set (match_operand:ILASX 0 "register_operand" "=f")
(ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f"))
(match_operand:ILASX 1 "register_operand" "f")))]
diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc
index fbe46833c9b..f0de80d767b 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
#define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du
#define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s
#define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d
-#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3
-#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3
+#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3
+#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3
#define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2
#define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2
#define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2
@@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
#define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si
#define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di
-#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3
-#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3
+#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3
+#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3
#define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2
#define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2
#define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 459ad30b9bb..4e4ddd515c9 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1668,7 +1668,7 @@ (define_insn "*norsi3_internal"
[(set_attr "type" "logical")
(set_attr "mode" "SI")])
-(define_insn "<optab>n<mode>"
+(define_insn "<optab>n<mode>3"
[(set (match_operand:X 0 "register_operand" "=r")
(neg_bitwise:X
(not:X (match_operand:X 1 "register_operand" "r"))
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 454cda47876..dcb667a6ce5 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -2344,7 +2344,7 @@ (define_insn_and_split "vec_concatv4sf"
}
[(set_attr "mode" "V4SF")])
-(define_insn "vandn<mode>3"
+(define_insn "andn<mode>3"
[(set (match_operand:LSX 0 "register_operand" "=f")
(and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f"))
(match_operand:LSX 2 "register_operand" "f")))]
@@ -3028,7 +3028,7 @@ (define_insn "lsx_vssrlrn_<hlsxfmt>_<lsxfmt>"
[(set_attr "type" "simd_int_arith")
(set_attr "mode" "<MODE>")])
-(define_insn "vorn<mode>3"
+(define_insn "iorn<mode>3"
[(set (match_operand:ILSX 0 "register_operand" "=f")
(ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f"))
(match_operand:ILSX 1 "register_operand" "f")))]
--
2.39.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] LoongArch: Use iorn and andn standard pattern names.
2024-07-27 8:54 [PATCH] LoongArch: Use iorn and andn standard pattern names Lulu Cheng
@ 2024-07-27 19:30 ` Andrew Pinski
2024-07-29 1:05 ` Lulu Cheng
0 siblings, 1 reply; 3+ messages in thread
From: Andrew Pinski @ 2024-07-27 19:30 UTC (permalink / raw)
To: Lulu Cheng; +Cc: gcc-patches, xry111, i, xuchenghua
On Sat, Jul 27, 2024 at 1:55 AM Lulu Cheng <chenglulu@loongson.cn> wrote:
>
> gcc/ChangeLog:
>
> * config/loongarch/lasx.md (xvandn<mode>3): Rename to ...
> (andn<mode>3): This.
> (xvorn<mode>3): Rename to ...
> (iorn<mode>3): This.
> * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v):
> Defined as the modified name.
> (CODE_FOR_lsx_vorn_v): Likewise.
> (CODE_FOR_lasx_xvandn_v): Likewise.
> (CODE_FOR_lasx_xvorn_v): Likewise.
> * config/loongarch/loongarch.md (<optab>n<mode>): Rename to ...
> (<optab>n<mode>3): This.
> * config/loongarch/lsx.md (vandn<mode>3): Rename to ...
> (andn<mode>3): This. .
> (vorn<mode>3): Rename to ...
> (iorn<mode>3): This.
You might want to add a testcase like I did for aarch64:
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658219.html .
Thanks,
Andrew Pinski
> ---
> gcc/config/loongarch/lasx.md | 4 ++--
> gcc/config/loongarch/loongarch-builtins.cc | 8 ++++----
> gcc/config/loongarch/loongarch.md | 2 +-
> gcc/config/loongarch/lsx.md | 4 ++--
> 4 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
> index 7bd61f8ed5b..c5fe04de86c 100644
> --- a/gcc/config/loongarch/lasx.md
> +++ b/gcc/config/loongarch/lasx.md
> @@ -2716,7 +2716,7 @@ (define_insn "lasx_vext2xv_d<u>_b<u>"
> (set_attr "mode" "V4DI")])
>
> ;; Extend loongson-sx to loongson-asx.
> -(define_insn "xvandn<mode>3"
> +(define_insn "andn<mode>3"
> [(set (match_operand:LASX 0 "register_operand" "=f")
> (and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f"))
> (match_operand:LASX 2 "register_operand" "f")))]
> @@ -4637,7 +4637,7 @@ (define_insn "lasx_xvssrlrn_<hlasxfmt>_<lasxfmt>"
> [(set_attr "type" "simd_int_arith")
> (set_attr "mode" "<MODE>")])
>
> -(define_insn "xvorn<mode>3"
> +(define_insn "iorn<mode>3"
> [(set (match_operand:ILASX 0 "register_operand" "=f")
> (ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f"))
> (match_operand:ILASX 1 "register_operand" "f")))]
> diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc
> index fbe46833c9b..f0de80d767b 100644
> --- a/gcc/config/loongarch/loongarch-builtins.cc
> +++ b/gcc/config/loongarch/loongarch-builtins.cc
> @@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
> #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du
> #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s
> #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d
> -#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3
> -#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3
> +#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3
> +#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3
> #define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2
> #define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2
> #define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2
> @@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
> #define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si
> #define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di
>
> -#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3
> -#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3
> +#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3
> +#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3
> #define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2
> #define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2
> #define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index 459ad30b9bb..4e4ddd515c9 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -1668,7 +1668,7 @@ (define_insn "*norsi3_internal"
> [(set_attr "type" "logical")
> (set_attr "mode" "SI")])
>
> -(define_insn "<optab>n<mode>"
> +(define_insn "<optab>n<mode>3"
> [(set (match_operand:X 0 "register_operand" "=r")
> (neg_bitwise:X
> (not:X (match_operand:X 1 "register_operand" "r"))
> diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
> index 454cda47876..dcb667a6ce5 100644
> --- a/gcc/config/loongarch/lsx.md
> +++ b/gcc/config/loongarch/lsx.md
> @@ -2344,7 +2344,7 @@ (define_insn_and_split "vec_concatv4sf"
> }
> [(set_attr "mode" "V4SF")])
>
> -(define_insn "vandn<mode>3"
> +(define_insn "andn<mode>3"
> [(set (match_operand:LSX 0 "register_operand" "=f")
> (and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f"))
> (match_operand:LSX 2 "register_operand" "f")))]
> @@ -3028,7 +3028,7 @@ (define_insn "lsx_vssrlrn_<hlsxfmt>_<lsxfmt>"
> [(set_attr "type" "simd_int_arith")
> (set_attr "mode" "<MODE>")])
>
> -(define_insn "vorn<mode>3"
> +(define_insn "iorn<mode>3"
> [(set (match_operand:ILSX 0 "register_operand" "=f")
> (ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f"))
> (match_operand:ILSX 1 "register_operand" "f")))]
> --
> 2.39.3
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] LoongArch: Use iorn and andn standard pattern names.
2024-07-27 19:30 ` Andrew Pinski
@ 2024-07-29 1:05 ` Lulu Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Lulu Cheng @ 2024-07-29 1:05 UTC (permalink / raw)
To: Andrew Pinski; +Cc: gcc-patches, xry111, i, xuchenghua
在 2024/7/28 上午3:30, Andrew Pinski 写道:
> On Sat, Jul 27, 2024 at 1:55 AM Lulu Cheng <chenglulu@loongson.cn> wrote:
>> gcc/ChangeLog:
>>
>> * config/loongarch/lasx.md (xvandn<mode>3): Rename to ...
>> (andn<mode>3): This.
>> (xvorn<mode>3): Rename to ...
>> (iorn<mode>3): This.
>> * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v):
>> Defined as the modified name.
>> (CODE_FOR_lsx_vorn_v): Likewise.
>> (CODE_FOR_lasx_xvandn_v): Likewise.
>> (CODE_FOR_lasx_xvorn_v): Likewise.
>> * config/loongarch/loongarch.md (<optab>n<mode>): Rename to ...
>> (<optab>n<mode>3): This.
>> * config/loongarch/lsx.md (vandn<mode>3): Rename to ...
>> (andn<mode>3): This. .
>> (vorn<mode>3): Rename to ...
>> (iorn<mode>3): This.
>
> You might want to add a testcase like I did for aarch64:
> https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658219.html .
>
> Thanks,
> Andrew Pinski
Ok, I'll add a test case for this modification.
Thanks.
>
>> ---
>> gcc/config/loongarch/lasx.md | 4 ++--
>> gcc/config/loongarch/loongarch-builtins.cc | 8 ++++----
>> gcc/config/loongarch/loongarch.md | 2 +-
>> gcc/config/loongarch/lsx.md | 4 ++--
>> 4 files changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
>> index 7bd61f8ed5b..c5fe04de86c 100644
>> --- a/gcc/config/loongarch/lasx.md
>> +++ b/gcc/config/loongarch/lasx.md
>> @@ -2716,7 +2716,7 @@ (define_insn "lasx_vext2xv_d<u>_b<u>"
>> (set_attr "mode" "V4DI")])
>>
>> ;; Extend loongson-sx to loongson-asx.
>> -(define_insn "xvandn<mode>3"
>> +(define_insn "andn<mode>3"
>> [(set (match_operand:LASX 0 "register_operand" "=f")
>> (and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f"))
>> (match_operand:LASX 2 "register_operand" "f")))]
>> @@ -4637,7 +4637,7 @@ (define_insn "lasx_xvssrlrn_<hlasxfmt>_<lasxfmt>"
>> [(set_attr "type" "simd_int_arith")
>> (set_attr "mode" "<MODE>")])
>>
>> -(define_insn "xvorn<mode>3"
>> +(define_insn "iorn<mode>3"
>> [(set (match_operand:ILASX 0 "register_operand" "=f")
>> (ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f"))
>> (match_operand:ILASX 1 "register_operand" "f")))]
>> diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc
>> index fbe46833c9b..f0de80d767b 100644
>> --- a/gcc/config/loongarch/loongarch-builtins.cc
>> +++ b/gcc/config/loongarch/loongarch-builtins.cc
>> @@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
>> #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du
>> #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s
>> #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d
>> -#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3
>> -#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3
>> +#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3
>> +#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3
>> #define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2
>> #define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2
>> #define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2
>> @@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
>> #define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si
>> #define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di
>>
>> -#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3
>> -#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3
>> +#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3
>> +#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3
>> #define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2
>> #define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2
>> #define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2
>> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
>> index 459ad30b9bb..4e4ddd515c9 100644
>> --- a/gcc/config/loongarch/loongarch.md
>> +++ b/gcc/config/loongarch/loongarch.md
>> @@ -1668,7 +1668,7 @@ (define_insn "*norsi3_internal"
>> [(set_attr "type" "logical")
>> (set_attr "mode" "SI")])
>>
>> -(define_insn "<optab>n<mode>"
>> +(define_insn "<optab>n<mode>3"
>> [(set (match_operand:X 0 "register_operand" "=r")
>> (neg_bitwise:X
>> (not:X (match_operand:X 1 "register_operand" "r"))
>> diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
>> index 454cda47876..dcb667a6ce5 100644
>> --- a/gcc/config/loongarch/lsx.md
>> +++ b/gcc/config/loongarch/lsx.md
>> @@ -2344,7 +2344,7 @@ (define_insn_and_split "vec_concatv4sf"
>> }
>> [(set_attr "mode" "V4SF")])
>>
>> -(define_insn "vandn<mode>3"
>> +(define_insn "andn<mode>3"
>> [(set (match_operand:LSX 0 "register_operand" "=f")
>> (and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f"))
>> (match_operand:LSX 2 "register_operand" "f")))]
>> @@ -3028,7 +3028,7 @@ (define_insn "lsx_vssrlrn_<hlsxfmt>_<lsxfmt>"
>> [(set_attr "type" "simd_int_arith")
>> (set_attr "mode" "<MODE>")])
>>
>> -(define_insn "vorn<mode>3"
>> +(define_insn "iorn<mode>3"
>> [(set (match_operand:ILSX 0 "register_operand" "=f")
>> (ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f"))
>> (match_operand:ILSX 1 "register_operand" "f")))]
>> --
>> 2.39.3
>>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-07-27 8:54 [PATCH] LoongArch: Use iorn and andn standard pattern names Lulu Cheng
2024-07-27 19:30 ` Andrew Pinski
2024-07-29 1:05 ` Lulu Cheng
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