diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 03ba8fc..589a6cb 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -8286,7 +8286,9 @@ is undefined if @var{a} is modified before using @var{b}.
 @code{asm} supports operand modifiers on operands (for example @samp{%k2} 
 instead of simply @samp{%2}). Typically these qualifiers are hardware 
 dependent. The list of supported modifiers for x86 is found at 
-@ref{x86Operandmodifiers,x86 Operand modifiers}.
+@ref{x86Operandmodifiers,x86 Operand modifiers}.  The list of supported
+modifiers for AArch64 is found at
+@ref{AArch64Operandmodifiers,AArch64 Operand modifiers}.
 
 If the C code that follows the @code{asm} makes no use of any of the output 
 operands, use @code{volatile} for the @code{asm} statement to prevent the 
@@ -8513,7 +8515,9 @@ optimizers may discard the @code{asm} statement as unneeded
 @code{asm} supports operand modifiers on operands (for example @samp{%k2} 
 instead of simply @samp{%2}). Typically these qualifiers are hardware 
 dependent. The list of supported modifiers for x86 is found at 
-@ref{x86Operandmodifiers,x86 Operand modifiers}.
+@ref{x86Operandmodifiers,x86 Operand modifiers}.  The list of supported
+modifiers for AArch64 is found at
+@ref{AArch64Operandmodifiers,AArch64 Operand modifiers}.
 
 In this example using the fictitious @code{combine} instruction, the 
 constraint @code{"0"} for input operand 1 says that it must occupy the same 
@@ -8681,6 +8685,71 @@ error:
 @}
 @end example
 
+@anchor{AArch64Operandmodifiers}
+@subsubsection AArch64 Operand Modifiers
+References to input, output, and goto operands in the assembler template
+of extended @code{asm} statements can use
+modifiers to affect the way the operands are formatted in
+the code output to the assembler.
+
+The table below descirbes the list of useful register operand modifiers which
+might be used in extended @code{asm}. It is not a complete list of modifiers
+supported by the AArch64 backend.
+
+@multitable {Modifier} {Print the opcode suffix for the size of the} {Operand}
+@headitem Modifier @tab Description @tab Operand
+@item @code{w}
+@tab Print 32-bit name of the general purpose register.
+@tab @code{%w0}
+@item @code{x}
+@tab Print 64-bit name of the general purpose register.
+@tab @code{%x0}
+@item @code{h}
+@tab Print 16-bit name of the scalar floating-point register.
+@tab @code{%h0}
+@item @code{s}
+@tab Print 32-bit name of the scalar floating-point register.
+@tab @code{%s0}
+@item @code{d}
+@tab Print 64-bit name of the scalar floating-point register.
+@tab @code{%d0}
+@item @code{q}
+@tab Print 128-bit name of the scalar floating-point register.
+@tab @code{%q0}
+@item @code{H}
+@tab Print the higher numbered 64-bit register name of a pair (TImode) of
+general purpose registers.
+@tab @code{%H0}
+@end multitable
+
+Without specifying any modifiers to a register operand, the default @code{x}
+register name is used for integer operands, @code{v} register name is used for
+floating pointer operands. For example:
+
+@example
+int load_int (int *ptr, int offset)
+@{
+  int  result;
+  asm ("ldr %0, [%1, %2]\n\t"
+       : "=r" (result)
+       : "r" (ptr), "r"(offset));
+  return result;
+@}
+@end example
+
+The following code will be generated:
+
+@smallexample
+ldr x0, [x0, x1]
+@end smallexample
+
+If proper modifier is used for the first operand @code{result}, say @code{w},
+it will generate the following code as one would expect:
+
+@smallexample
+ldr w0, [x0, x1]
+@end smallexample
+
 @anchor{x86Operandmodifiers}
 @subsubsection x86 Operand Modifiers