From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 58921 invoked by alias); 5 Sep 2017 17:53:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 58912 invoked by uid 89); 5 Sep 2017 17:53:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=Hx-languages-length:1765 X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 05 Sep 2017 17:53:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E23E513D5; Tue, 5 Sep 2017 10:53:06 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A36873F3E1; Tue, 5 Sep 2017 10:53:05 -0700 (PDT) Message-ID: <59AEE480.5070909@foss.arm.com> Date: Tue, 05 Sep 2017 17:53:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Bernd Edlinger , Wilco Dijkstra , Christophe Lyon CC: Ramana Radhakrishnan , GCC Patches , Richard Earnshaw , nd Subject: Re: [PING**2] [PATCH, ARM] Further improve stack usage on sha512 (PR 77308) References: <59AD6894.7010605@foss.arm.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2017-09/txt/msg00292.txt.bz2 On 05/09/17 18:48, Bernd Edlinger wrote: > On 09/05/17 17:02, Wilco Dijkstra wrote: >> Bernd Edlinger wrote: >> >>> Combine creates an invalid insn out of these two insns: >> Yes it looks like a latent bug. We need to use arm_general_register_operand >> as arm_adddi3/subdi3 only allow integer registers. You don't need a new predicate >> s_register_operand_nv. Also I'd prefer something like arm_general_adddi_operand. >> > Thanks, attached is a patch following your suggestion. > >> + "TARGET_32BIT && ((!TARGET_NEON && !TARGET_IWMMXT) || reload_completed)" >> >> The split condition for adddi3 now looks more accurate indeed, although we could >> remove the !TARGET_NEON from the split condition as this is always true given >> arm_adddi3 uses "TARGET_32BIT && !TARGET_NEON". >> > No, the split condition does not begin with "&& TARGET_32BIT...". > Therefore the split is enabled in TARGET_NEON after reload_completed. > And it is invoked from adddi3_neon for all alternatives without vfp > registers: > > switch (which_alternative) > { > case 0: /* fall through */ > case 3: return "vadd.i64\t%P0, %P1, %P2"; > case 1: return "#"; > case 2: return "#"; > case 4: return "#"; > case 5: return "#"; > case 6: return "#"; > > > >> Also there are more cases, a quick grep suggests *anddi_notdi_di has the same issue. >> > Yes, that pattern can be cleaned up in a follow-up patch. > Note this splitter is invoked from bicdi3_neon as well. > However I think anddi_notdi_di should be safe as long as it is enabled > after reload_completed (which is probably a bug). > Thanks, that's what I had in mind in my other reply. This is ok if testing comes back ok. Kyrill > Bernd. > >> Wilco >>