* [PATCH, GCC/ARM, 0/2] Add support for Armv8.1-M Mainline scalar shifts
@ 2019-11-14 14:19 Mihail Ionescu
2019-11-14 14:19 ` [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline Mihail Ionescu
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Mihail Ionescu @ 2019-11-14 14:19 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 403 bytes --]
Hi,
This is a patch series to introduce the Armv8.1-M Mainline scalar shift
instructions to the arm backend.
Mihail Ionescu (2)
[PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline
[PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline
Regards,
Mihail
Entire patch series attached to cover letter.
[-- Attachment #2: all-patches.tar.gz --]
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline 2019-11-14 14:19 [PATCH, GCC/ARM, 0/2] Add support for Armv8.1-M Mainline scalar shifts Mihail Ionescu @ 2019-11-14 14:19 ` Mihail Ionescu 2019-11-14 14:25 ` [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) " Mihail Ionescu ` (4 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: Mihail Ionescu @ 2019-11-14 14:19 UTC (permalink / raw) To: gcc-patches; +Cc: kyrylo.tkachov, richard.earnshaw [-- Attachment #1: Type: text/plain, Size: 5231 bytes --] Hi, This patch adds the new scalar shift instructions for Armv8.1-M Mainline to the arm backend. This patch is adding the following instructions: ASRL (reg) LSLL (reg) ChangeLog entry are as follow: *** gcc/ChangeLog *** 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2019-11-14 Sudakshina Das <sudi.das@arm.com> * config/arm/arm.h (TARGET_MVE): New macro for MVE support. * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_MVE. (ashrdi3): Generate thumb2_asrl for TARGET_MVE. * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd register pairs for doubleword quantities for ARMv8.1M-Mainline. * config/arm/thumb2.md (thumb2_asrl): New. (thumb2_lsll): Likewise. *** gcc/testsuite/ChangeLog *** 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2019-11-14 Sudakshina Das <sudi.das@arm.com> * gcc.target/arm/armv8_1m-shift-reg_1.c: New test. Testsuite shows no regression when run for arm-none-eabi targets. Is this ok for trunk? Thanks Mihail ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index be51df7d14738bc1addeab8ac5a3806778106bce..bf788087a30343269b30cf7054ec29212ad9c572 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -24454,14 +24454,15 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* We allow almost any value to be stored in the general registers. Restrict doubleword quantities to even register pairs in ARM state - so that we can use ldrd. Do not allow very large Neon structure - opaque modes in general registers; they would use too many. */ + so that we can use ldrd and Armv8.1-M Mainline instructions. + Do not allow very large Neon structure opaque modes in general + registers; they would use too many. */ if (regno <= LAST_ARM_REGNUM) { if (ARM_NUM_REGS (mode) > 4) return false; - if (TARGET_THUMB2) + if (TARGET_THUMB2 && !TARGET_HAVE_MVE) return true; return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a91a4b941c3f9d2c3d443f9f4639069ae953fb3b..b735f858a6a5c94d02a6765c1b349cdcb5e77ee3 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3503,6 +3503,22 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + if (TARGET_HAVE_MVE) + { + if (!reg_or_int_operand (operands[2], SImode)) + operands[2] = force_reg (SImode, operands[2]); + + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (REG_P (operands[2])) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_lsll (operands[0], operands[2])); + DONE; + } + } + arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); @@ -3530,6 +3546,16 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (TARGET_HAVE_MVE && REG_P (operands[2])) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_asrl (operands[0], operands[2])); + DONE; + } + arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index c08dab233784bd1cbaae147ece795058d2ef234f..3a716ea954ac55b2081121248b930b7f11520ffa 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1645,3 +1645,19 @@ } [(set_attr "predicable" "yes")] ) + +(define_insn "thumb2_asrl" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ashiftrt:DI (match_dup 0) + (match_operand:SI 1 "arm_general_register_operand" "r")))] + "TARGET_HAVE_MVE" + "asrl%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "thumb2_lsll" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ashift:DI (match_dup 0) + (match_operand:SI 1 "arm_general_register_operand" "r")))] + "TARGET_HAVE_MVE" + "lsll%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c new file mode 100644 index 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ + +long long longval2; +int intval2; + +long long int +asrl_reg () +{ + return (longval2 >> intval2); +} + +long long unsigned int +lsll_reg (long long unsigned longval1, int intval1) +{ + return (longval1 << intval1); +} + +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ [-- Attachment #2: diff0.patch --] [-- Type: text/plain, Size: 4135 bytes --] diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index be51df7d14738bc1addeab8ac5a3806778106bce..bf788087a30343269b30cf7054ec29212ad9c572 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -24454,14 +24454,15 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* We allow almost any value to be stored in the general registers. Restrict doubleword quantities to even register pairs in ARM state - so that we can use ldrd. Do not allow very large Neon structure - opaque modes in general registers; they would use too many. */ + so that we can use ldrd and Armv8.1-M Mainline instructions. + Do not allow very large Neon structure opaque modes in general + registers; they would use too many. */ if (regno <= LAST_ARM_REGNUM) { if (ARM_NUM_REGS (mode) > 4) return false; - if (TARGET_THUMB2) + if (TARGET_THUMB2 && !TARGET_HAVE_MVE) return true; return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a91a4b941c3f9d2c3d443f9f4639069ae953fb3b..b735f858a6a5c94d02a6765c1b349cdcb5e77ee3 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3503,6 +3503,22 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + if (TARGET_HAVE_MVE) + { + if (!reg_or_int_operand (operands[2], SImode)) + operands[2] = force_reg (SImode, operands[2]); + + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (REG_P (operands[2])) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_lsll (operands[0], operands[2])); + DONE; + } + } + arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); @@ -3530,6 +3546,16 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (TARGET_HAVE_MVE && REG_P (operands[2])) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_asrl (operands[0], operands[2])); + DONE; + } + arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index c08dab233784bd1cbaae147ece795058d2ef234f..3a716ea954ac55b2081121248b930b7f11520ffa 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1645,3 +1645,19 @@ } [(set_attr "predicable" "yes")] ) + +(define_insn "thumb2_asrl" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ashiftrt:DI (match_dup 0) + (match_operand:SI 1 "arm_general_register_operand" "r")))] + "TARGET_HAVE_MVE" + "asrl%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "thumb2_lsll" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ashift:DI (match_dup 0) + (match_operand:SI 1 "arm_general_register_operand" "r")))] + "TARGET_HAVE_MVE" + "lsll%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c new file mode 100644 index 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ + +long long longval2; +int intval2; + +long long int +asrl_reg () +{ + return (longval2 >> intval2); +} + +long long unsigned int +lsll_reg (long long unsigned longval1, int intval1) +{ + return (longval1 << intval1); +} + +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline 2019-11-14 14:19 [PATCH, GCC/ARM, 0/2] Add support for Armv8.1-M Mainline scalar shifts Mihail Ionescu 2019-11-14 14:19 ` [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline Mihail Ionescu @ 2019-11-14 14:25 ` Mihail Ionescu [not found] ` <bf86297a-b750-4593-a235-c10c1510b176@VE1EUR03FT054.eop-EUR03.prod.protection.outlook.com> ` (3 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: Mihail Ionescu @ 2019-11-14 14:25 UTC (permalink / raw) To: gcc-patches; +Cc: nd [-- Attachment #1: Type: text/plain, Size: 6744 bytes --] Hi, This is part of a series of patches where I am trying to add new instructions for Armv8.1-M Mainline to the arm backend. This patch is adding the following instructions: ASRL (imm) LSLL (imm) LSRL (imm) ChangeLog entry are as follow: *** gcc/ChangeLog *** 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2019-11-14 Sudakshina Das <sudi.das@arm.com> * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg and valid immediate. (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. (lshrdi3): Generate thumb2_lsrl for valid immediates. * config/arm/constraints.md (Pg): New. * config/arm/predicates.md (long_shift_imm): New. (arm_reg_or_long_shift_imm): Likewise. * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. (thumb2_lsll): Likewise. (thumb2_lsrl): New. *** gcc/testsuite/ChangeLog *** 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2019-11-14 Sudakshina Das <sudi.das@arm.com> * gcc.target/arm/armv8_1m-shift-imm_1.c: New test. Testsuite shows no regression when run for arm-none-eabi targets. Is this ok for trunk? Thanks Mihail ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b735f858a6a5c94d02a6765c1b349cdcb5e77ee3..82f4a5573d43925fb7638b9078a06699df38f88c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3509,8 +3509,8 @@ operands[2] = force_reg (SImode, operands[2]); /* Armv8.1-M Mainline double shifts are not expanded. */ - if (REG_P (operands[2])) - { + if (arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) + { if (!reg_overlap_mentioned_p(operands[0], operands[1])) emit_insn (gen_movdi (operands[0], operands[1])); @@ -3547,7 +3547,8 @@ "TARGET_32BIT" " /* Armv8.1-M Mainline double shifts are not expanded. */ - if (TARGET_HAVE_MVE && REG_P (operands[2])) + if (TARGET_HAVE_MVE + && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) { if (!reg_overlap_mentioned_p(operands[0], operands[1])) emit_insn (gen_movdi (operands[0], operands[1])); @@ -3580,6 +3581,17 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (TARGET_HAVE_MVE + && long_shift_imm (operands[2], GET_MODE (operands[2]))) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_lsrl (operands[0], operands[2])); + DONE; + } + arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index b76de81b85c8ce7a2ca484a750b908b7ca64600a..d807818c8499a6a65837f1ed0487e45947f68199 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -35,7 +35,7 @@ ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz -;; in all states: Pf +;; in all states: Pf, Pg ;; The following memory constraints have been used: ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us @@ -187,6 +187,11 @@ && !is_mm_consume (memmodel_from_int (ival)) && !is_mm_release (memmodel_from_int (ival))"))) +(define_constraint "Pg" + "@internal In Thumb-2 state a constant in range 1 to 32" + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32"))) + (define_constraint "Ps" "@internal In Thumb-2 state a constant in the range -255 to +255" (and (match_code "const_int") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 69c10c06ff405e19efa172217a08a512c66cb902..ef5b0303d4424981347287865efb3cca85e56f36 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -322,6 +322,15 @@ && (UINTVAL (XEXP (op, 1)) < 32)"))) (match_test "mode == GET_MODE (op)"))) +;; True for Armv8.1-M Mainline long shift instructions. +(define_predicate "long_shift_imm" + (match_test "satisfies_constraint_Pg (op)")) + +(define_predicate "arm_reg_or_long_shift_imm" + (ior (match_test "TARGET_THUMB2 + && arm_general_register_operand (op, GET_MODE (op))") + (match_test "satisfies_constraint_Pg (op)"))) + ;; True for MULT, to identify which variant of shift_operator is in use. (define_special_predicate "mult_operator" (match_code "mult")) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 3a716ea954ac55b2081121248b930b7f11520ffa..af486d07f428030257855381ff72c32a885b506f 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1649,7 +1649,7 @@ (define_insn "thumb2_asrl" [(set (match_operand:DI 0 "arm_general_register_operand" "+r") (ashiftrt:DI (match_dup 0) - (match_operand:SI 1 "arm_general_register_operand" "r")))] + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] "TARGET_HAVE_MVE" "asrl%?\\t%Q0, %R0, %1" [(set_attr "predicable" "yes")]) @@ -1657,7 +1657,15 @@ (define_insn "thumb2_lsll" [(set (match_operand:DI 0 "arm_general_register_operand" "+r") (ashift:DI (match_dup 0) - (match_operand:SI 1 "arm_general_register_operand" "r")))] + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] "TARGET_HAVE_MVE" "lsll%?\\t%Q0, %R0, %1" [(set_attr "predicable" "yes")]) + +(define_insn "thumb2_lsrl" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (lshiftrt:DI (match_dup 0) + (match_operand:SI 1 "long_shift_imm" "Pg")))] + "TARGET_HAVE_MVE" + "lsrl%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c new file mode 100644 index 0000000000000000000000000000000000000000..5ffa3769e6ba42466242d3038857734e87b2f1fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ + +long long longval1; +long long unsigned longval2; + +long long int +asrl_imm () +{ + return (longval1 >> 14); +} + +long long unsigned int +lsrl_imm () +{ + return (longval2 >> 14); +} + +long long int +lsll_imm (long long int longval3) +{ + return (longval3 << 14); +} + +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */ +/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */ +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */ [-- Attachment #2: diff1.patch --] [-- Type: text/plain, Size: 5534 bytes --] diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b735f858a6a5c94d02a6765c1b349cdcb5e77ee3..82f4a5573d43925fb7638b9078a06699df38f88c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3509,8 +3509,8 @@ operands[2] = force_reg (SImode, operands[2]); /* Armv8.1-M Mainline double shifts are not expanded. */ - if (REG_P (operands[2])) - { + if (arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) + { if (!reg_overlap_mentioned_p(operands[0], operands[1])) emit_insn (gen_movdi (operands[0], operands[1])); @@ -3547,7 +3547,8 @@ "TARGET_32BIT" " /* Armv8.1-M Mainline double shifts are not expanded. */ - if (TARGET_HAVE_MVE && REG_P (operands[2])) + if (TARGET_HAVE_MVE + && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) { if (!reg_overlap_mentioned_p(operands[0], operands[1])) emit_insn (gen_movdi (operands[0], operands[1])); @@ -3580,6 +3581,17 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (TARGET_HAVE_MVE + && long_shift_imm (operands[2], GET_MODE (operands[2]))) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_lsrl (operands[0], operands[2])); + DONE; + } + arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index b76de81b85c8ce7a2ca484a750b908b7ca64600a..d807818c8499a6a65837f1ed0487e45947f68199 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -35,7 +35,7 @@ ;; Dt, Dp, Dz, Tu ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz -;; in all states: Pf +;; in all states: Pf, Pg ;; The following memory constraints have been used: ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us @@ -187,6 +187,11 @@ && !is_mm_consume (memmodel_from_int (ival)) && !is_mm_release (memmodel_from_int (ival))"))) +(define_constraint "Pg" + "@internal In Thumb-2 state a constant in range 1 to 32" + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32"))) + (define_constraint "Ps" "@internal In Thumb-2 state a constant in the range -255 to +255" (and (match_code "const_int") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 69c10c06ff405e19efa172217a08a512c66cb902..ef5b0303d4424981347287865efb3cca85e56f36 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -322,6 +322,15 @@ && (UINTVAL (XEXP (op, 1)) < 32)"))) (match_test "mode == GET_MODE (op)"))) +;; True for Armv8.1-M Mainline long shift instructions. +(define_predicate "long_shift_imm" + (match_test "satisfies_constraint_Pg (op)")) + +(define_predicate "arm_reg_or_long_shift_imm" + (ior (match_test "TARGET_THUMB2 + && arm_general_register_operand (op, GET_MODE (op))") + (match_test "satisfies_constraint_Pg (op)"))) + ;; True for MULT, to identify which variant of shift_operator is in use. (define_special_predicate "mult_operator" (match_code "mult")) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 3a716ea954ac55b2081121248b930b7f11520ffa..af486d07f428030257855381ff72c32a885b506f 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1649,7 +1649,7 @@ (define_insn "thumb2_asrl" [(set (match_operand:DI 0 "arm_general_register_operand" "+r") (ashiftrt:DI (match_dup 0) - (match_operand:SI 1 "arm_general_register_operand" "r")))] + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] "TARGET_HAVE_MVE" "asrl%?\\t%Q0, %R0, %1" [(set_attr "predicable" "yes")]) @@ -1657,7 +1657,15 @@ (define_insn "thumb2_lsll" [(set (match_operand:DI 0 "arm_general_register_operand" "+r") (ashift:DI (match_dup 0) - (match_operand:SI 1 "arm_general_register_operand" "r")))] + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] "TARGET_HAVE_MVE" "lsll%?\\t%Q0, %R0, %1" [(set_attr "predicable" "yes")]) + +(define_insn "thumb2_lsrl" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (lshiftrt:DI (match_dup 0) + (match_operand:SI 1 "long_shift_imm" "Pg")))] + "TARGET_HAVE_MVE" + "lsrl%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c new file mode 100644 index 0000000000000000000000000000000000000000..5ffa3769e6ba42466242d3038857734e87b2f1fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ + +long long longval1; +long long unsigned longval2; + +long long int +asrl_imm () +{ + return (longval1 >> 14); +} + +long long unsigned int +lsrl_imm () +{ + return (longval2 >> 14); +} + +long long int +lsll_imm (long long int longval3) +{ + return (longval3 << 14); +} + +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */ +/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */ +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */ ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <bf86297a-b750-4593-a235-c10c1510b176@VE1EUR03FT054.eop-EUR03.prod.protection.outlook.com>]
* Re: [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline [not found] ` <bf86297a-b750-4593-a235-c10c1510b176@VE1EUR03FT054.eop-EUR03.prod.protection.outlook.com> @ 2019-12-11 17:51 ` Kyrill Tkachov 2019-12-18 13:26 ` Mihail Ionescu 0 siblings, 1 reply; 10+ messages in thread From: Kyrill Tkachov @ 2019-12-11 17:51 UTC (permalink / raw) To: Mihail Ionescu, gcc-patches; +Cc: Richard Earnshaw Hi Mihail, On 11/14/19 1:54 PM, Mihail Ionescu wrote: > Hi, > > This patch adds the new scalar shift instructions for Armv8.1-M > Mainline to the arm backend. > This patch is adding the following instructions: > > ASRL (reg) > LSLL (reg) > Sorry for the delay, very busy time for GCC development :( > > ChangeLog entry are as follow: > > *** gcc/ChangeLog *** > > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > >        * config/arm/arm.h (TARGET_MVE): New macro for MVE support. I don't see this hunk in the patch... There's a lot of v8.1-M-related patches in flight. Is it defined elsewhere? >        * config/arm/arm.md (ashldi3): Generate thumb2_lsll for > TARGET_MVE. >        (ashrdi3): Generate thumb2_asrl for TARGET_MVE. >        * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd >        register pairs for doubleword quantities for ARMv8.1M-Mainline. >        * config/arm/thumb2.md (thumb2_asrl): New. >        (thumb2_lsll): Likewise. > > *** gcc/testsuite/ChangeLog *** > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > >        * gcc.target/arm/armv8_1m-shift-reg_1.c: New test. > > Testsuite shows no regression when run for arm-none-eabi targets. > > Is this ok for trunk? > > Thanks > Mihail > > > ###############    Attachment also inlined for ease of reply   > ############### > > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index > be51df7d14738bc1addeab8ac5a3806778106bce..bf788087a30343269b30cf7054ec29212ad9c572 > 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -24454,14 +24454,15 @@ arm_hard_regno_mode_ok (unsigned int regno, > machine_mode mode) > >   /* We allow almost any value to be stored in the general registers. >      Restrict doubleword quantities to even register pairs in ARM state > -    so that we can use ldrd. Do not allow very large Neon structure > -    opaque modes in general registers; they would use too many. */ > +    so that we can use ldrd and Armv8.1-M Mainline instructions. > +    Do not allow very large Neon structure opaque modes in general > +    registers; they would use too many. */ This comment now reads: "Restrict doubleword quantities to even register pairs in ARM state  so that we can use ldrd and Armv8.1-M Mainline instructions." Armv8.1-M Mainline is not ARM mode though, so please clarify this comment further. Looks ok to me otherwise (I may even have merged this with the second patch, but I'm not complaining about keeping it simple :) ) Thanks, Kyrill >   if (regno <= LAST_ARM_REGNUM) >     { >       if (ARM_NUM_REGS (mode) > 4) >         return false; > > -     if (TARGET_THUMB2) > +     if (TARGET_THUMB2 && !TARGET_HAVE_MVE) >         return true; > >       return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) > != 0); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index > a91a4b941c3f9d2c3d443f9f4639069ae953fb3b..b735f858a6a5c94d02a6765c1b349cdcb5e77ee3 > 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -3503,6 +3503,22 @@ >                    (match_operand:SI 2 "reg_or_int_operand")))] >   "TARGET_32BIT" >   " > + if (TARGET_HAVE_MVE) > +   { > +     if (!reg_or_int_operand (operands[2], SImode)) > +       operands[2] = force_reg (SImode, operands[2]); > + > +     /* Armv8.1-M Mainline double shifts are not expanded. */ > +     if (REG_P (operands[2])) > +      { > +        if (!reg_overlap_mentioned_p(operands[0], operands[1])) > +          emit_insn (gen_movdi (operands[0], operands[1])); > + > +        emit_insn (gen_thumb2_lsll (operands[0], operands[2])); > +        DONE; > +      } > +   } > + >   arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], >                                  operands[2], gen_reg_rtx (SImode), >                                  gen_reg_rtx (SImode)); > @@ -3530,6 +3546,16 @@ >                      (match_operand:SI 2 "reg_or_int_operand")))] >   "TARGET_32BIT" >   " > + /* Armv8.1-M Mainline double shifts are not expanded. */ > + if (TARGET_HAVE_MVE && REG_P (operands[2])) > +   { > +     if (!reg_overlap_mentioned_p(operands[0], operands[1])) > +      emit_insn (gen_movdi (operands[0], operands[1])); > + > +     emit_insn (gen_thumb2_asrl (operands[0], operands[2])); > +     DONE; > +   } > + >   arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], >                                  operands[2], gen_reg_rtx (SImode), >                                  gen_reg_rtx (SImode)); > diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > index > c08dab233784bd1cbaae147ece795058d2ef234f..3a716ea954ac55b2081121248b930b7f11520ffa > 100644 > --- a/gcc/config/arm/thumb2.md > +++ b/gcc/config/arm/thumb2.md > @@ -1645,3 +1645,19 @@ >   } >   [(set_attr "predicable" "yes")] >  ) > + > +(define_insn "thumb2_asrl" > + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > +      (ashiftrt:DI (match_dup 0) > +                   (match_operand:SI 1 > "arm_general_register_operand" "r")))] > + "TARGET_HAVE_MVE" > + "asrl%?\\t%Q0, %R0, %1" > + [(set_attr "predicable" "yes")]) > + > +(define_insn "thumb2_lsll" > + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > +      (ashift:DI (match_dup 0) > +                 (match_operand:SI 1 "arm_general_register_operand" > "r")))] > + "TARGET_HAVE_MVE" > + "lsll%?\\t%Q0, %R0, %1" > + [(set_attr "predicable" "yes")]) > diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ > + > +long long longval2; > +int intval2; > + > +long long int > +asrl_reg () > +{ > + return (longval2 >> intval2); > +} > + > +long long unsigned int > +lsll_reg (long long unsigned longval1, int intval1) > +{ > + return (longval1 << intval1); > +} > + > +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" > } } */ > +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" > } } */ > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline 2019-12-11 17:51 ` [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) " Kyrill Tkachov @ 2019-12-18 13:26 ` Mihail Ionescu 2020-01-17 11:21 ` Kyrill Tkachov 0 siblings, 1 reply; 10+ messages in thread From: Mihail Ionescu @ 2019-12-18 13:26 UTC (permalink / raw) To: Kyrill Tkachov, gcc-patches; +Cc: Richard Earnshaw [-- Attachment #1: Type: text/plain, Size: 8222 bytes --] Hi Kyrill, On 12/11/2019 05:50 PM, Kyrill Tkachov wrote: > Hi Mihail, > > On 11/14/19 1:54 PM, Mihail Ionescu wrote: >> Hi, >> >> This patch adds the new scalar shift instructions for Armv8.1-M >> Mainline to the arm backend. >> This patch is adding the following instructions: >> >> ASRL (reg) >> LSLL (reg) >> > > Sorry for the delay, very busy time for GCC development :( > > >> >> ChangeLog entry are as follow: >> >> *** gcc/ChangeLog *** >> >> >> 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> >> 2019-11-14 Sudakshina Das <sudi.das@arm.com> >> >>        * config/arm/arm.h (TARGET_MVE): New macro for MVE support. > > > I don't see this hunk in the patch... There's a lot of v8.1-M-related > patches in flight. Is it defined elsewhere? Thanks for having a look at this. Yes, I forgot to remove that bit from the ChangeLog and mention that the patch depends on the Armv8.1-M MVE CLI -- https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00641.htm which introduces the required TARGET_* macros needed. I've updated the ChangeLog to reflect that: *** gcc/ChangeLog *** 2019-12-18 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2019-12-18 Sudakshina Das <sudi.das@arm.com> * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE. (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE. * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd register pairs for doubleword quantities for ARMv8.1M-Mainline. * config/arm/thumb2.md (thumb2_asrl): New. (thumb2_lsll): Likewise. > > >>        * config/arm/arm.md (ashldi3): Generate thumb2_lsll for >> TARGET_MVE. >>        (ashrdi3): Generate thumb2_asrl for TARGET_MVE. >>        * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd >>        register pairs for doubleword quantities for ARMv8.1M-Mainline. >>        * config/arm/thumb2.md (thumb2_asrl): New. >>        (thumb2_lsll): Likewise. >> >> *** gcc/testsuite/ChangeLog *** >> >> 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> >> 2019-11-14 Sudakshina Das <sudi.das@arm.com> >> >>        * gcc.target/arm/armv8_1m-shift-reg_1.c: New test. >> >> Testsuite shows no regression when run for arm-none-eabi targets. >> >> Is this ok for trunk? >> >> Thanks >> Mihail >> >> >> ###############    Attachment also inlined for ease of reply >> ############### >> >> >> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c >> index >> be51df7d14738bc1addeab8ac5a3806778106bce..bf788087a30343269b30cf7054ec29212ad9c572 >> 100644 >> --- a/gcc/config/arm/arm.c >> +++ b/gcc/config/arm/arm.c >> @@ -24454,14 +24454,15 @@ arm_hard_regno_mode_ok (unsigned int regno, >> machine_mode mode) >> >>   /* We allow almost any value to be stored in the general registers. >>      Restrict doubleword quantities to even register pairs in ARM state >> -    so that we can use ldrd. Do not allow very large Neon structure >> -    opaque modes in general registers; they would use too many. */ >> +    so that we can use ldrd and Armv8.1-M Mainline instructions. >> +    Do not allow very large Neon structure opaque modes in general >> +    registers; they would use too many. */ > > > This comment now reads: > > "Restrict doubleword quantities to even register pairs in ARM state >  so that we can use ldrd and Armv8.1-M Mainline instructions." > > Armv8.1-M Mainline is not ARM mode though, so please clarify this > comment further. > > Looks ok to me otherwise (I may even have merged this with the second > patch, but I'm not complaining about keeping it simple :) ) > > Thanks, > > Kyrill > I've now updated the comment to read: "Restrict doubleword quantities to even register pairs in ARM state so that we can use ldrd. The same restriction applies for MVE." Regards, Mihail > >>   if (regno <= LAST_ARM_REGNUM) >>     { >>       if (ARM_NUM_REGS (mode) > 4) >>         return false; >> >> -     if (TARGET_THUMB2) >> +     if (TARGET_THUMB2 && !TARGET_HAVE_MVE) >>         return true; >> >>       return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) >> != 0); >> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md >> index >> a91a4b941c3f9d2c3d443f9f4639069ae953fb3b..b735f858a6a5c94d02a6765c1b349cdcb5e77ee3 >> 100644 >> --- a/gcc/config/arm/arm.md >> +++ b/gcc/config/arm/arm.md >> @@ -3503,6 +3503,22 @@ >>                    (match_operand:SI 2 "reg_or_int_operand")))] >>   "TARGET_32BIT" >>   " >> + if (TARGET_HAVE_MVE) >> +   { >> +     if (!reg_or_int_operand (operands[2], SImode)) >> +       operands[2] = force_reg (SImode, operands[2]); >> + >> +     /* Armv8.1-M Mainline double shifts are not expanded. */ >> +     if (REG_P (operands[2])) >> +      { >> +        if (!reg_overlap_mentioned_p(operands[0], operands[1])) >> +          emit_insn (gen_movdi (operands[0], operands[1])); >> + >> +        emit_insn (gen_thumb2_lsll (operands[0], operands[2])); >> +        DONE; >> +      } >> +   } >> + >>   arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], >>                                  operands[2], gen_reg_rtx (SImode), >>                                  gen_reg_rtx (SImode)); >> @@ -3530,6 +3546,16 @@ >>                      (match_operand:SI 2 "reg_or_int_operand")))] >>   "TARGET_32BIT" >>   " >> + /* Armv8.1-M Mainline double shifts are not expanded. */ >> + if (TARGET_HAVE_MVE && REG_P (operands[2])) >> +   { >> +     if (!reg_overlap_mentioned_p(operands[0], operands[1])) >> +      emit_insn (gen_movdi (operands[0], operands[1])); >> + >> +     emit_insn (gen_thumb2_asrl (operands[0], operands[2])); >> +     DONE; >> +   } >> + >>   arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], >>                                  operands[2], gen_reg_rtx (SImode), >>                                  gen_reg_rtx (SImode)); >> diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md >> index >> c08dab233784bd1cbaae147ece795058d2ef234f..3a716ea954ac55b2081121248b930b7f11520ffa >> 100644 >> --- a/gcc/config/arm/thumb2.md >> +++ b/gcc/config/arm/thumb2.md >> @@ -1645,3 +1645,19 @@ >>   } >>   [(set_attr "predicable" "yes")] >>  ) >> + >> +(define_insn "thumb2_asrl" >> + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >> +      (ashiftrt:DI (match_dup 0) >> +                   (match_operand:SI 1 >> "arm_general_register_operand" "r")))] >> + "TARGET_HAVE_MVE" >> + "asrl%?\\t%Q0, %R0, %1" >> + [(set_attr "predicable" "yes")]) >> + >> +(define_insn "thumb2_lsll" >> + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >> +      (ashift:DI (match_dup 0) >> +                 (match_operand:SI 1 "arm_general_register_operand" >> "r")))] >> + "TARGET_HAVE_MVE" >> + "lsll%?\\t%Q0, %R0, %1" >> + [(set_attr "predicable" "yes")]) >> diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c >> b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c >> new file mode 100644 >> index >> 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 >> >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c >> @@ -0,0 +1,20 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ >> + >> +long long longval2; >> +int intval2; >> + >> +long long int >> +asrl_reg () >> +{ >> + return (longval2 >> intval2); >> +} >> + >> +long long unsigned int >> +lsll_reg (long long unsigned longval1, int intval1) >> +{ >> + return (longval1 << intval1); >> +} >> + >> +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" >> } } */ >> +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" >> } } */ >> [-- Attachment #2: diff.patch --] [-- Type: text/x-patch, Size: 4194 bytes --] diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3fbd54c59ea1de107235d36ad2474e0cbc8452bb..1ae4a843bb4f9ad196a8a96c0b8b0396fa7cd8a0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -24828,14 +24828,16 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* We allow almost any value to be stored in the general registers. Restrict doubleword quantities to even register pairs in ARM state - so that we can use ldrd. Do not allow very large Neon structure - opaque modes in general registers; they would use too many. */ + so that we can use ldrd. The same restriction applies for MVE + in order to support Armv8.1-M Mainline instructions. + Do not allow very large Neon structure opaque modes in general + registers; they would use too many. */ if (regno <= LAST_ARM_REGNUM) { if (ARM_NUM_REGS (mode) > 4) return false; - if (TARGET_THUMB2) + if (TARGET_THUMB2 && !TARGET_HAVE_MVE) return true; return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index d3ac2ff54b62206be3c70461b98c5e122ff3b340..fb813ca38a4ed45661a8dab915400ffa75a18ed7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4102,6 +4102,22 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + if (TARGET_HAVE_MVE) + { + if (!reg_or_int_operand (operands[2], SImode)) + operands[2] = force_reg (SImode, operands[2]); + + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (REG_P (operands[2])) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_lsll (operands[0], operands[2])); + DONE; + } + } + arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); @@ -4129,6 +4145,16 @@ (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " + /* Armv8.1-M Mainline double shifts are not expanded. */ + if (TARGET_HAVE_MVE && REG_P (operands[2])) + { + if (!reg_overlap_mentioned_p(operands[0], operands[1])) + emit_insn (gen_movdi (operands[0], operands[1])); + + emit_insn (gen_thumb2_asrl (operands[0], operands[2])); + DONE; + } + arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], operands[2], gen_reg_rtx (SImode), gen_reg_rtx (SImode)); diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 8c08629a9e5e0621073132dc0e41a788b3581273..18b15fa1272cfc3f09f758f260adbd589bc3c05f 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1626,3 +1626,19 @@ } [(set_attr "predicable" "yes")] ) + +(define_insn "thumb2_asrl" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ashiftrt:DI (match_dup 0) + (match_operand:SI 1 "arm_general_register_operand" "r")))] + "TARGET_HAVE_MVE" + "asrl%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "thumb2_lsll" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ashift:DI (match_dup 0) + (match_operand:SI 1 "arm_general_register_operand" "r")))] + "TARGET_HAVE_MVE" + "lsll%?\\t%Q0, %R0, %1" + [(set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c new file mode 100644 index 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ + +long long longval2; +int intval2; + +long long int +asrl_reg () +{ + return (longval2 >> intval2); +} + +long long unsigned int +lsll_reg (long long unsigned longval1, int intval1) +{ + return (longval1 << intval1); +} + +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline 2019-12-18 13:26 ` Mihail Ionescu @ 2020-01-17 11:21 ` Kyrill Tkachov 0 siblings, 0 replies; 10+ messages in thread From: Kyrill Tkachov @ 2020-01-17 11:21 UTC (permalink / raw) To: Mihail Ionescu, Kyrill Tkachov, gcc-patches; +Cc: Richard Earnshaw On 12/18/19 1:23 PM, Mihail Ionescu wrote: > > > Hi Kyrill, > > On 12/11/2019 05:50 PM, Kyrill Tkachov wrote: > > Hi Mihail, > > > > On 11/14/19 1:54 PM, Mihail Ionescu wrote: > >> Hi, > >> > >> This patch adds the new scalar shift instructions for Armv8.1-M > >> Mainline to the arm backend. > >> This patch is adding the following instructions: > >> > >> ASRL (reg) > >> LSLL (reg) > >> > > > > Sorry for the delay, very busy time for GCC development :( > > > > > >> > >> ChangeLog entry are as follow: > >> > >> *** gcc/ChangeLog *** > >> > >> > >> 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > >> 2019-11-14 Sudakshina Das <sudi.das@arm.com> > >> > >>        * config/arm/arm.h (TARGET_MVE): New macro for MVE support. > > > > > > I don't see this hunk in the patch... There's a lot of v8.1-M-related > > patches in flight. Is it defined elsewhere? > > Thanks for having a look at this. > Yes, I forgot to remove that bit from the ChangeLog and mention that the > patch depends on the Armv8.1-M MVE CLI -- > https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00641.htm which introduces > the required TARGET_* macros needed. I've updated the ChangeLog to > reflect that: > > *** gcc/ChangeLog *** > > > 2019-12-18 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-12-18 Sudakshina Das <sudi.das@arm.com> > >        * config/arm/arm.md (ashldi3): Generate thumb2_lsll for > TARGET_HAVE_MVE. >        (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE. >        * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd >        register pairs for doubleword quantities for ARMv8.1M-Mainline. >        * config/arm/thumb2.md (thumb2_asrl): New. >        (thumb2_lsll): Likewise. > > > > > > >>        * config/arm/arm.md (ashldi3): Generate thumb2_lsll for > >> TARGET_MVE. > >>        (ashrdi3): Generate thumb2_asrl for TARGET_MVE. > >>        * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd > >>        register pairs for doubleword quantities for ARMv8.1M-Mainline. > >>        * config/arm/thumb2.md (thumb2_asrl): New. > >>        (thumb2_lsll): Likewise. > >> > >> *** gcc/testsuite/ChangeLog *** > >> > >> 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > >> 2019-11-14 Sudakshina Das <sudi.das@arm.com> > >> > >>        * gcc.target/arm/armv8_1m-shift-reg_1.c: New test. > >> > >> Testsuite shows no regression when run for arm-none-eabi targets. > >> > >> Is this ok for trunk? > >> > >> Thanks > >> Mihail > >> > >> > >> ###############    Attachment also inlined for ease of reply > >> ############### > >> > >> > >> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > >> index > >> > be51df7d14738bc1addeab8ac5a3806778106bce..bf788087a30343269b30cf7054ec29212ad9c572 > > >> 100644 > >> --- a/gcc/config/arm/arm.c > >> +++ b/gcc/config/arm/arm.c > >> @@ -24454,14 +24454,15 @@ arm_hard_regno_mode_ok (unsigned int regno, > >> machine_mode mode) > >> > >>   /* We allow almost any value to be stored in the general registers. > >>      Restrict doubleword quantities to even register pairs in ARM > state > >> -    so that we can use ldrd. Do not allow very large Neon structure > >> -    opaque modes in general registers; they would use too many. */ > >> +    so that we can use ldrd and Armv8.1-M Mainline instructions. > >> +    Do not allow very large Neon structure opaque modes in general > >> +    registers; they would use too many. */ > > > > > > This comment now reads: > > > > "Restrict doubleword quantities to even register pairs in ARM state > >  so that we can use ldrd and Armv8.1-M Mainline instructions." > > > > Armv8.1-M Mainline is not ARM mode though, so please clarify this > > comment further. > > > > Looks ok to me otherwise (I may even have merged this with the second > > patch, but I'm not complaining about keeping it simple :) ) > > > > Thanks, > > > > Kyrill > > > > I've now updated the comment to read: > "Restrict doubleword quantities to even register pairs in ARM state > so that we can use ldrd. The same restriction applies for MVE." > Ok. Thanks, Kyril > > Regards, > Mihail > > > > >>   if (regno <= LAST_ARM_REGNUM) > >>     { > >>       if (ARM_NUM_REGS (mode) > 4) > >>         return false; > >> > >> -     if (TARGET_THUMB2) > >> +     if (TARGET_THUMB2 && !TARGET_HAVE_MVE) > >>         return true; > >> > >>       return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) > >> != 0); > >> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > >> index > >> > a91a4b941c3f9d2c3d443f9f4639069ae953fb3b..b735f858a6a5c94d02a6765c1b349cdcb5e77ee3 > > >> 100644 > >> --- a/gcc/config/arm/arm.md > >> +++ b/gcc/config/arm/arm.md > >> @@ -3503,6 +3503,22 @@ > >>                    (match_operand:SI 2 "reg_or_int_operand")))] > >>   "TARGET_32BIT" > >>   " > >> + if (TARGET_HAVE_MVE) > >> +   { > >> +     if (!reg_or_int_operand (operands[2], SImode)) > >> +       operands[2] = force_reg (SImode, operands[2]); > >> + > >> +     /* Armv8.1-M Mainline double shifts are not expanded. */ > >> +     if (REG_P (operands[2])) > >> +      { > >> +        if (!reg_overlap_mentioned_p(operands[0], operands[1])) > >> +          emit_insn (gen_movdi (operands[0], operands[1])); > >> + > >> +        emit_insn (gen_thumb2_lsll (operands[0], operands[2])); > >> +        DONE; > >> +      } > >> +   } > >> + > >>   arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], > >>                                  operands[2], gen_reg_rtx (SImode), > >>                                  gen_reg_rtx (SImode)); > >> @@ -3530,6 +3546,16 @@ > >>                      (match_operand:SI 2 "reg_or_int_operand")))] > >>   "TARGET_32BIT" > >>   " > >> + /* Armv8.1-M Mainline double shifts are not expanded. */ > >> + if (TARGET_HAVE_MVE && REG_P (operands[2])) > >> +   { > >> +     if (!reg_overlap_mentioned_p(operands[0], operands[1])) > >> +      emit_insn (gen_movdi (operands[0], operands[1])); > >> + > >> +     emit_insn (gen_thumb2_asrl (operands[0], operands[2])); > >> +     DONE; > >> +   } > >> + > >>   arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], > >>                                  operands[2], gen_reg_rtx (SImode), > >>                                  gen_reg_rtx (SImode)); > >> diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > >> index > >> > c08dab233784bd1cbaae147ece795058d2ef234f..3a716ea954ac55b2081121248b930b7f11520ffa > > >> 100644 > >> --- a/gcc/config/arm/thumb2.md > >> +++ b/gcc/config/arm/thumb2.md > >> @@ -1645,3 +1645,19 @@ > >>   } > >>   [(set_attr "predicable" "yes")] > >>  ) > >> + > >> +(define_insn "thumb2_asrl" > >> + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > >> +      (ashiftrt:DI (match_dup 0) > >> +                   (match_operand:SI 1 > >> "arm_general_register_operand" "r")))] > >> + "TARGET_HAVE_MVE" > >> + "asrl%?\\t%Q0, %R0, %1" > >> + [(set_attr "predicable" "yes")]) > >> + > >> +(define_insn "thumb2_lsll" > >> + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > >> +      (ashift:DI (match_dup 0) > >> +                 (match_operand:SI 1 "arm_general_register_operand" > >> "r")))] > >> + "TARGET_HAVE_MVE" > >> + "lsll%?\\t%Q0, %R0, %1" > >> + [(set_attr "predicable" "yes")]) > >> diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > >> b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > >> new file mode 100644 > >> index > >> > 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 > > >> > >> --- /dev/null > >> +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > >> @@ -0,0 +1,20 @@ > >> +/* { dg-do compile } */ > >> +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" > } */ > >> + > >> +long long longval2; > >> +int intval2; > >> + > >> +long long int > >> +asrl_reg () > >> +{ > >> + return (longval2 >> intval2); > >> +} > >> + > >> +long long unsigned int > >> +lsll_reg (long long unsigned longval1, int intval1) > >> +{ > >> + return (longval1 << intval1); > >> +} > >> + > >> +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" > >> } } */ > >> +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" > >> } } */ > >> ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <1066f99d-b2cf-4a6a-bc55-6ba86fc88220@DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com>]
* Re: [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline [not found] ` <1066f99d-b2cf-4a6a-bc55-6ba86fc88220@DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com> @ 2019-12-11 17:54 ` Kyrill Tkachov 0 siblings, 0 replies; 10+ messages in thread From: Kyrill Tkachov @ 2019-12-11 17:54 UTC (permalink / raw) To: Mihail Ionescu, gcc-patches; +Cc: nd Hi Mihail, On 11/14/19 1:54 PM, Mihail Ionescu wrote: > Hi, > > This is part of a series of patches where I am trying to add new > instructions for Armv8.1-M Mainline to the arm backend. > This patch is adding the following instructions: > > ASRL (imm) > LSLL (imm) > LSRL (imm) > > > ChangeLog entry are as follow: > > *** gcc/ChangeLog *** > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > >        * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg >        and valid immediate. >        (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. >        (lshrdi3): Generate thumb2_lsrl for valid immediates. >        * config/arm/constraints.md (Pg): New. >        * config/arm/predicates.md (long_shift_imm): New. >        (arm_reg_or_long_shift_imm): Likewise. >        * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. >        (thumb2_lsll): Likewise. >        (thumb2_lsrl): New. > > *** gcc/testsuite/ChangeLog *** > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > >        * gcc.target/arm/armv8_1m-shift-imm_1.c: New test. > > Testsuite shows no regression when run for arm-none-eabi targets. > > Is this ok for trunk? > This is ok once the prerequisites are in. Thanks, Kyrill > Thanks > Mihail > > > ###############    Attachment also inlined for ease of reply   > ############### > > > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index > b735f858a6a5c94d02a6765c1b349cdcb5e77ee3..82f4a5573d43925fb7638b9078a06699df38f88c > 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -3509,8 +3509,8 @@ >         operands[2] = force_reg (SImode, operands[2]); > >       /* Armv8.1-M Mainline double shifts are not expanded. */ > -     if (REG_P (operands[2])) > -      { > +     if (arm_reg_or_long_shift_imm (operands[2], GET_MODE > (operands[2]))) > +       { >           if (!reg_overlap_mentioned_p(operands[0], operands[1])) >             emit_insn (gen_movdi (operands[0], operands[1])); > > @@ -3547,7 +3547,8 @@ >   "TARGET_32BIT" >   " >   /* Armv8.1-M Mainline double shifts are not expanded. */ > - if (TARGET_HAVE_MVE && REG_P (operands[2])) > + if (TARGET_HAVE_MVE > +     && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) >     { >       if (!reg_overlap_mentioned_p(operands[0], operands[1])) >         emit_insn (gen_movdi (operands[0], operands[1])); > @@ -3580,6 +3581,17 @@ >                      (match_operand:SI 2 "reg_or_int_operand")))] >   "TARGET_32BIT" >   " > + /* Armv8.1-M Mainline double shifts are not expanded. */ > + if (TARGET_HAVE_MVE > +   && long_shift_imm (operands[2], GET_MODE (operands[2]))) > +   { > +     if (!reg_overlap_mentioned_p(operands[0], operands[1])) > +       emit_insn (gen_movdi (operands[0], operands[1])); > + > +     emit_insn (gen_thumb2_lsrl (operands[0], operands[2])); > +     DONE; > +   } > + >   arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1], >                                  operands[2], gen_reg_rtx (SImode), >                                  gen_reg_rtx (SImode)); > diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md > index > b76de81b85c8ce7a2ca484a750b908b7ca64600a..d807818c8499a6a65837f1ed0487e45947f68199 > 100644 > --- a/gcc/config/arm/constraints.md > +++ b/gcc/config/arm/constraints.md > @@ -35,7 +35,7 @@ >  ;;                      Dt, Dp, Dz, Tu >  ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe >  ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz > -;; in all states: Pf > +;; in all states: Pf, Pg > >  ;; The following memory constraints have been used: >  ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us > @@ -187,6 +187,11 @@ >                     && !is_mm_consume (memmodel_from_int (ival)) >                     && !is_mm_release (memmodel_from_int (ival))"))) > > +(define_constraint "Pg" > + "@internal In Thumb-2 state a constant in range 1 to 32" > + (and (match_code "const_int") > +      (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32"))) > + >  (define_constraint "Ps" >   "@internal In Thumb-2 state a constant in the range -255 to +255" >   (and (match_code "const_int") > diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md > index > 69c10c06ff405e19efa172217a08a512c66cb902..ef5b0303d4424981347287865efb3cca85e56f36 > 100644 > --- a/gcc/config/arm/predicates.md > +++ b/gcc/config/arm/predicates.md > @@ -322,6 +322,15 @@ >                               && (UINTVAL (XEXP (op, 1)) < 32)"))) >        (match_test "mode == GET_MODE (op)"))) > > +;; True for Armv8.1-M Mainline long shift instructions. > +(define_predicate "long_shift_imm" > + (match_test "satisfies_constraint_Pg (op)")) > + > +(define_predicate "arm_reg_or_long_shift_imm" > + (ior (match_test "TARGET_THUMB2 > +                  && arm_general_register_operand (op, GET_MODE (op))") > +      (match_test "satisfies_constraint_Pg (op)"))) > + >  ;; True for MULT, to identify which variant of shift_operator is in use. >  (define_special_predicate "mult_operator" >   (match_code "mult")) > diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > index > 3a716ea954ac55b2081121248b930b7f11520ffa..af486d07f428030257855381ff72c32a885b506f > 100644 > --- a/gcc/config/arm/thumb2.md > +++ b/gcc/config/arm/thumb2.md > @@ -1649,7 +1649,7 @@ >  (define_insn "thumb2_asrl" >   [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >         (ashiftrt:DI (match_dup 0) > -                   (match_operand:SI 1 > "arm_general_register_operand" "r")))] > +                   (match_operand:SI 1 "arm_reg_or_long_shift_imm" > "rPg")))] >   "TARGET_HAVE_MVE" >   "asrl%?\\t%Q0, %R0, %1" >   [(set_attr "predicable" "yes")]) > @@ -1657,7 +1657,15 @@ >  (define_insn "thumb2_lsll" >   [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >         (ashift:DI (match_dup 0) > -                 (match_operand:SI 1 "arm_general_register_operand" > "r")))] > +                 (match_operand:SI 1 "arm_reg_or_long_shift_imm" > "rPg")))] >   "TARGET_HAVE_MVE" >   "lsll%?\\t%Q0, %R0, %1" >   [(set_attr "predicable" "yes")]) > + > +(define_insn "thumb2_lsrl" > + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > +      (lshiftrt:DI (match_dup 0) > +                   (match_operand:SI 1 "long_shift_imm" "Pg")))] > + "TARGET_HAVE_MVE" > + "lsrl%?\\t%Q0, %R0, %1" > + [(set_attr "predicable" "yes")]) > diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c > b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..5ffa3769e6ba42466242d3038857734e87b2f1fc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ > + > +long long longval1; > +long long unsigned longval2; > + > +long long int > +asrl_imm () > +{ > + return (longval1 >> 14); > +} > + > +long long unsigned int > +lsrl_imm () > +{ > + return (longval2 >> 14); > +} > + > +long long int > +lsll_imm (long long int longval3) > +{ > + return (longval3 << 14); > +} > + > +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */ > +/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */ > +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */ > ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <5dcd627a.1c69fb81.97b2a.8f10SMTPIN_ADDED_MISSING@mx.google.com>]
* Re: [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline [not found] ` <5dcd627a.1c69fb81.97b2a.8f10SMTPIN_ADDED_MISSING@mx.google.com> @ 2020-01-20 13:24 ` Christophe Lyon 0 siblings, 0 replies; 10+ messages in thread From: Christophe Lyon @ 2020-01-20 13:24 UTC (permalink / raw) To: Mihail Ionescu; +Cc: gcc Patches, Kyrylo Tkachov, Richard Earnshaw On Thu, 14 Nov 2019 at 15:19, Mihail Ionescu <mihail.ionescu@foss.arm.com> wrote: > > Hi, > > This patch adds the new scalar shift instructions for Armv8.1-M > Mainline to the arm backend. > This patch is adding the following instructions: > > ASRL (reg) > LSLL (reg) > > > ChangeLog entry are as follow: > > *** gcc/ChangeLog *** > > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > > * config/arm/arm.h (TARGET_MVE): New macro for MVE support. > * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_MVE. > (ashrdi3): Generate thumb2_asrl for TARGET_MVE. > * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd > register pairs for doubleword quantities for ARMv8.1M-Mainline. > * config/arm/thumb2.md (thumb2_asrl): New. > (thumb2_lsll): Likewise. > > *** gcc/testsuite/ChangeLog *** > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > > * gcc.target/arm/armv8_1m-shift-reg_1.c: New test. > > Testsuite shows no regression when run for arm-none-eabi targets. > > Is this ok for trunk? > > Thanks > Mihail > > > ############### Attachment also inlined for ease of reply ############### > > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index be51df7d14738bc1addeab8ac5a3806778106bce..bf788087a30343269b30cf7054ec29212ad9c572 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -24454,14 +24454,15 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode) > > /* We allow almost any value to be stored in the general registers. > Restrict doubleword quantities to even register pairs in ARM state > - so that we can use ldrd. Do not allow very large Neon structure > - opaque modes in general registers; they would use too many. */ > + so that we can use ldrd and Armv8.1-M Mainline instructions. > + Do not allow very large Neon structure opaque modes in general > + registers; they would use too many. */ > if (regno <= LAST_ARM_REGNUM) > { > if (ARM_NUM_REGS (mode) > 4) > return false; > > - if (TARGET_THUMB2) > + if (TARGET_THUMB2 && !TARGET_HAVE_MVE) > return true; > > return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index a91a4b941c3f9d2c3d443f9f4639069ae953fb3b..b735f858a6a5c94d02a6765c1b349cdcb5e77ee3 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -3503,6 +3503,22 @@ > (match_operand:SI 2 "reg_or_int_operand")))] > "TARGET_32BIT" > " > + if (TARGET_HAVE_MVE) > + { > + if (!reg_or_int_operand (operands[2], SImode)) > + operands[2] = force_reg (SImode, operands[2]); > + > + /* Armv8.1-M Mainline double shifts are not expanded. */ > + if (REG_P (operands[2])) > + { > + if (!reg_overlap_mentioned_p(operands[0], operands[1])) > + emit_insn (gen_movdi (operands[0], operands[1])); > + > + emit_insn (gen_thumb2_lsll (operands[0], operands[2])); > + DONE; > + } > + } > + > arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1], > operands[2], gen_reg_rtx (SImode), > gen_reg_rtx (SImode)); > @@ -3530,6 +3546,16 @@ > (match_operand:SI 2 "reg_or_int_operand")))] > "TARGET_32BIT" > " > + /* Armv8.1-M Mainline double shifts are not expanded. */ > + if (TARGET_HAVE_MVE && REG_P (operands[2])) > + { > + if (!reg_overlap_mentioned_p(operands[0], operands[1])) > + emit_insn (gen_movdi (operands[0], operands[1])); > + > + emit_insn (gen_thumb2_asrl (operands[0], operands[2])); > + DONE; > + } > + > arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1], > operands[2], gen_reg_rtx (SImode), > gen_reg_rtx (SImode)); > diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > index c08dab233784bd1cbaae147ece795058d2ef234f..3a716ea954ac55b2081121248b930b7f11520ffa 100644 > --- a/gcc/config/arm/thumb2.md > +++ b/gcc/config/arm/thumb2.md > @@ -1645,3 +1645,19 @@ > } > [(set_attr "predicable" "yes")] > ) > + > +(define_insn "thumb2_asrl" > + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > + (ashiftrt:DI (match_dup 0) > + (match_operand:SI 1 "arm_general_register_operand" "r")))] > + "TARGET_HAVE_MVE" > + "asrl%?\\t%Q0, %R0, %1" > + [(set_attr "predicable" "yes")]) > + > +(define_insn "thumb2_lsll" > + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > + (ashift:DI (match_dup 0) > + (match_operand:SI 1 "arm_general_register_operand" "r")))] > + "TARGET_HAVE_MVE" > + "lsll%?\\t%Q0, %R0, %1" > + [(set_attr "predicable" "yes")]) Hi, > diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > new file mode 100644 > index 0000000000000000000000000000000000000000..a97e9d687ef66e9642dd1d735125c8ee941fb151 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ This new test fails to compile when GCC is configured to default to arm mode (or rather, not configured to default to thumb mode): cc1: error: target CPU does not support ARM mode compiler exited with status 1 FAIL: gcc.target/arm/armv8_1m-shift-reg-1.c (test for excess errors) Excess errors: cc1: error: target CPU does not support ARM mode gcc.target/arm/armv8_1m-shift-reg-1.c: output file does not exist M-profile targets need -mthumb. Did you test with gcc configured --with-thumb only? Thanks, Christophe > + > +long long longval2; > +int intval2; > + > +long long int > +asrl_reg () > +{ > + return (longval2 >> intval2); > +} > + > +long long unsigned int > +lsll_reg (long long unsigned longval1, int intval1) > +{ > + return (longval1 << intval1); > +} > + > +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ > +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */ > ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <5dcd628a.1c69fb81.4a132.905dSMTPIN_ADDED_MISSING@mx.google.com>]
* Re: [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline [not found] ` <5dcd628a.1c69fb81.4a132.905dSMTPIN_ADDED_MISSING@mx.google.com> @ 2020-01-20 13:25 ` Christophe Lyon 2020-01-20 19:37 ` Mihail Ionescu 0 siblings, 1 reply; 10+ messages in thread From: Christophe Lyon @ 2020-01-20 13:25 UTC (permalink / raw) To: Mihail Ionescu; +Cc: gcc Patches, nd On Thu, 14 Nov 2019 at 15:19, Mihail Ionescu <mihail.ionescu@foss.arm.com> wrote: > > Hi, > > This is part of a series of patches where I am trying to add new > instructions for Armv8.1-M Mainline to the arm backend. > This patch is adding the following instructions: > > ASRL (imm) > LSLL (imm) > LSRL (imm) > > > ChangeLog entry are as follow: > > *** gcc/ChangeLog *** > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > > * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg > and valid immediate. > (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. > (lshrdi3): Generate thumb2_lsrl for valid immediates. > * config/arm/constraints.md (Pg): New. > * config/arm/predicates.md (long_shift_imm): New. > (arm_reg_or_long_shift_imm): Likewise. > * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. > (thumb2_lsll): Likewise. > (thumb2_lsrl): New. > > *** gcc/testsuite/ChangeLog *** > > 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> > 2019-11-14 Sudakshina Das <sudi.das@arm.com> > > * gcc.target/arm/armv8_1m-shift-imm_1.c: New test. > > Testsuite shows no regression when run for arm-none-eabi targets. > > Is this ok for trunk? > > Thanks > Mihail > > > ############### Attachment also inlined for ease of reply ############### > > > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index b735f858a6a5c94d02a6765c1b349cdcb5e77ee3..82f4a5573d43925fb7638b9078a06699df38f88c 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -3509,8 +3509,8 @@ > operands[2] = force_reg (SImode, operands[2]); > > /* Armv8.1-M Mainline double shifts are not expanded. */ > - if (REG_P (operands[2])) > - { > + if (arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) > + { > if (!reg_overlap_mentioned_p(operands[0], operands[1])) > emit_insn (gen_movdi (operands[0], operands[1])); > > @@ -3547,7 +3547,8 @@ > "TARGET_32BIT" > " > /* Armv8.1-M Mainline double shifts are not expanded. */ > - if (TARGET_HAVE_MVE && REG_P (operands[2])) > + if (TARGET_HAVE_MVE > + && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) > { > if (!reg_overlap_mentioned_p(operands[0], operands[1])) > emit_insn (gen_movdi (operands[0], operands[1])); > @@ -3580,6 +3581,17 @@ > (match_operand:SI 2 "reg_or_int_operand")))] > "TARGET_32BIT" > " > + /* Armv8.1-M Mainline double shifts are not expanded. */ > + if (TARGET_HAVE_MVE > + && long_shift_imm (operands[2], GET_MODE (operands[2]))) > + { > + if (!reg_overlap_mentioned_p(operands[0], operands[1])) > + emit_insn (gen_movdi (operands[0], operands[1])); > + > + emit_insn (gen_thumb2_lsrl (operands[0], operands[2])); > + DONE; > + } > + > arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1], > operands[2], gen_reg_rtx (SImode), > gen_reg_rtx (SImode)); > diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md > index b76de81b85c8ce7a2ca484a750b908b7ca64600a..d807818c8499a6a65837f1ed0487e45947f68199 100644 > --- a/gcc/config/arm/constraints.md > +++ b/gcc/config/arm/constraints.md > @@ -35,7 +35,7 @@ > ;; Dt, Dp, Dz, Tu > ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe > ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz > -;; in all states: Pf > +;; in all states: Pf, Pg > > ;; The following memory constraints have been used: > ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us > @@ -187,6 +187,11 @@ > && !is_mm_consume (memmodel_from_int (ival)) > && !is_mm_release (memmodel_from_int (ival))"))) > > +(define_constraint "Pg" > + "@internal In Thumb-2 state a constant in range 1 to 32" > + (and (match_code "const_int") > + (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32"))) > + > (define_constraint "Ps" > "@internal In Thumb-2 state a constant in the range -255 to +255" > (and (match_code "const_int") > diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md > index 69c10c06ff405e19efa172217a08a512c66cb902..ef5b0303d4424981347287865efb3cca85e56f36 100644 > --- a/gcc/config/arm/predicates.md > +++ b/gcc/config/arm/predicates.md > @@ -322,6 +322,15 @@ > && (UINTVAL (XEXP (op, 1)) < 32)"))) > (match_test "mode == GET_MODE (op)"))) > > +;; True for Armv8.1-M Mainline long shift instructions. > +(define_predicate "long_shift_imm" > + (match_test "satisfies_constraint_Pg (op)")) > + > +(define_predicate "arm_reg_or_long_shift_imm" > + (ior (match_test "TARGET_THUMB2 > + && arm_general_register_operand (op, GET_MODE (op))") > + (match_test "satisfies_constraint_Pg (op)"))) > + > ;; True for MULT, to identify which variant of shift_operator is in use. > (define_special_predicate "mult_operator" > (match_code "mult")) > diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > index 3a716ea954ac55b2081121248b930b7f11520ffa..af486d07f428030257855381ff72c32a885b506f 100644 > --- a/gcc/config/arm/thumb2.md > +++ b/gcc/config/arm/thumb2.md > @@ -1649,7 +1649,7 @@ > (define_insn "thumb2_asrl" > [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > (ashiftrt:DI (match_dup 0) > - (match_operand:SI 1 "arm_general_register_operand" "r")))] > + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] > "TARGET_HAVE_MVE" > "asrl%?\\t%Q0, %R0, %1" > [(set_attr "predicable" "yes")]) > @@ -1657,7 +1657,15 @@ > (define_insn "thumb2_lsll" > [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > (ashift:DI (match_dup 0) > - (match_operand:SI 1 "arm_general_register_operand" "r")))] > + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] > "TARGET_HAVE_MVE" > "lsll%?\\t%Q0, %R0, %1" > [(set_attr "predicable" "yes")]) > + > +(define_insn "thumb2_lsrl" > + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") > + (lshiftrt:DI (match_dup 0) > + (match_operand:SI 1 "long_shift_imm" "Pg")))] > + "TARGET_HAVE_MVE" > + "lsrl%?\\t%Q0, %R0, %1" > + [(set_attr "predicable" "yes")]) > diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c > new file mode 100644 > index 0000000000000000000000000000000000000000..5ffa3769e6ba42466242d3038857734e87b2f1fc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ Hi, Same problem as in patch 1/2: missing -mthumb. Thanks, Christophe > + > +long long longval1; > +long long unsigned longval2; > + > +long long int > +asrl_imm () > +{ > + return (longval1 >> 14); > +} > + > +long long unsigned int > +lsrl_imm () > +{ > + return (longval2 >> 14); > +} > + > +long long int > +lsll_imm (long long int longval3) > +{ > + return (longval3 << 14); > +} > + > +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */ > +/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */ > +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */ > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline 2020-01-20 13:25 ` [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) " Christophe Lyon @ 2020-01-20 19:37 ` Mihail Ionescu 0 siblings, 0 replies; 10+ messages in thread From: Mihail Ionescu @ 2020-01-20 19:37 UTC (permalink / raw) To: gcc-patches Hi Christophe, On 01/20/2020 01:19 PM, Christophe Lyon wrote: > On Thu, 14 Nov 2019 at 15:19, Mihail Ionescu > <mihail.ionescu@foss.arm.com> wrote: >> >> Hi, >> >> This is part of a series of patches where I am trying to add new >> instructions for Armv8.1-M Mainline to the arm backend. >> This patch is adding the following instructions: >> >> ASRL (imm) >> LSLL (imm) >> LSRL (imm) >> >> >> ChangeLog entry are as follow: >> >> *** gcc/ChangeLog *** >> >> 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> >> 2019-11-14 Sudakshina Das <sudi.das@arm.com> >> >> * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg >> and valid immediate. >> (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. >> (lshrdi3): Generate thumb2_lsrl for valid immediates. >> * config/arm/constraints.md (Pg): New. >> * config/arm/predicates.md (long_shift_imm): New. >> (arm_reg_or_long_shift_imm): Likewise. >> * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. >> (thumb2_lsll): Likewise. >> (thumb2_lsrl): New. >> >> *** gcc/testsuite/ChangeLog *** >> >> 2019-11-14 Mihail-Calin Ionescu <mihail.ionescu@arm.com> >> 2019-11-14 Sudakshina Das <sudi.das@arm.com> >> >> * gcc.target/arm/armv8_1m-shift-imm_1.c: New test. >> >> Testsuite shows no regression when run for arm-none-eabi targets. >> >> Is this ok for trunk? >> >> Thanks >> Mihail >> >> >> ############### Attachment also inlined for ease of reply ############### >> >> >> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md >> index b735f858a6a5c94d02a6765c1b349cdcb5e77ee3..82f4a5573d43925fb7638b9078a06699df38f88c 100644 >> --- a/gcc/config/arm/arm.md >> +++ b/gcc/config/arm/arm.md >> @@ -3509,8 +3509,8 @@ >> operands[2] = force_reg (SImode, operands[2]); >> >> /* Armv8.1-M Mainline double shifts are not expanded. */ >> - if (REG_P (operands[2])) >> - { >> + if (arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) >> + { >> if (!reg_overlap_mentioned_p(operands[0], operands[1])) >> emit_insn (gen_movdi (operands[0], operands[1])); >> >> @@ -3547,7 +3547,8 @@ >> "TARGET_32BIT" >> " >> /* Armv8.1-M Mainline double shifts are not expanded. */ >> - if (TARGET_HAVE_MVE && REG_P (operands[2])) >> + if (TARGET_HAVE_MVE >> + && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))) >> { >> if (!reg_overlap_mentioned_p(operands[0], operands[1])) >> emit_insn (gen_movdi (operands[0], operands[1])); >> @@ -3580,6 +3581,17 @@ >> (match_operand:SI 2 "reg_or_int_operand")))] >> "TARGET_32BIT" >> " >> + /* Armv8.1-M Mainline double shifts are not expanded. */ >> + if (TARGET_HAVE_MVE >> + && long_shift_imm (operands[2], GET_MODE (operands[2]))) >> + { >> + if (!reg_overlap_mentioned_p(operands[0], operands[1])) >> + emit_insn (gen_movdi (operands[0], operands[1])); >> + >> + emit_insn (gen_thumb2_lsrl (operands[0], operands[2])); >> + DONE; >> + } >> + >> arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1], >> operands[2], gen_reg_rtx (SImode), >> gen_reg_rtx (SImode)); >> diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md >> index b76de81b85c8ce7a2ca484a750b908b7ca64600a..d807818c8499a6a65837f1ed0487e45947f68199 100644 >> --- a/gcc/config/arm/constraints.md >> +++ b/gcc/config/arm/constraints.md >> @@ -35,7 +35,7 @@ >> ;; Dt, Dp, Dz, Tu >> ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe >> ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz >> -;; in all states: Pf >> +;; in all states: Pf, Pg >> >> ;; The following memory constraints have been used: >> ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us >> @@ -187,6 +187,11 @@ >> && !is_mm_consume (memmodel_from_int (ival)) >> && !is_mm_release (memmodel_from_int (ival))"))) >> >> +(define_constraint "Pg" >> + "@internal In Thumb-2 state a constant in range 1 to 32" >> + (and (match_code "const_int") >> + (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32"))) >> + >> (define_constraint "Ps" >> "@internal In Thumb-2 state a constant in the range -255 to +255" >> (and (match_code "const_int") >> diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md >> index 69c10c06ff405e19efa172217a08a512c66cb902..ef5b0303d4424981347287865efb3cca85e56f36 100644 >> --- a/gcc/config/arm/predicates.md >> +++ b/gcc/config/arm/predicates.md >> @@ -322,6 +322,15 @@ >> && (UINTVAL (XEXP (op, 1)) < 32)"))) >> (match_test "mode == GET_MODE (op)"))) >> >> +;; True for Armv8.1-M Mainline long shift instructions. >> +(define_predicate "long_shift_imm" >> + (match_test "satisfies_constraint_Pg (op)")) >> + >> +(define_predicate "arm_reg_or_long_shift_imm" >> + (ior (match_test "TARGET_THUMB2 >> + && arm_general_register_operand (op, GET_MODE (op))") >> + (match_test "satisfies_constraint_Pg (op)"))) >> + >> ;; True for MULT, to identify which variant of shift_operator is in use. >> (define_special_predicate "mult_operator" >> (match_code "mult")) >> diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md >> index 3a716ea954ac55b2081121248b930b7f11520ffa..af486d07f428030257855381ff72c32a885b506f 100644 >> --- a/gcc/config/arm/thumb2.md >> +++ b/gcc/config/arm/thumb2.md >> @@ -1649,7 +1649,7 @@ >> (define_insn "thumb2_asrl" >> [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >> (ashiftrt:DI (match_dup 0) >> - (match_operand:SI 1 "arm_general_register_operand" "r")))] >> + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] >> "TARGET_HAVE_MVE" >> "asrl%?\\t%Q0, %R0, %1" >> [(set_attr "predicable" "yes")]) >> @@ -1657,7 +1657,15 @@ >> (define_insn "thumb2_lsll" >> [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >> (ashift:DI (match_dup 0) >> - (match_operand:SI 1 "arm_general_register_operand" "r")))] >> + (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))] >> "TARGET_HAVE_MVE" >> "lsll%?\\t%Q0, %R0, %1" >> [(set_attr "predicable" "yes")]) >> + >> +(define_insn "thumb2_lsrl" >> + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") >> + (lshiftrt:DI (match_dup 0) >> + (match_operand:SI 1 "long_shift_imm" "Pg")))] >> + "TARGET_HAVE_MVE" >> + "lsrl%?\\t%Q0, %R0, %1" >> + [(set_attr "predicable" "yes")]) >> diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c >> new file mode 100644 >> index 0000000000000000000000000000000000000000..5ffa3769e6ba42466242d3038857734e87b2f1fc >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c >> @@ -0,0 +1,27 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */ > > Hi, > > Same problem as in patch 1/2: missing -mthumb. > > Thanks, > > Christophe > I've addressed the issue in this patch: https://gcc.gnu.org/ml/gcc-patches/2020-01/msg01254.html Regards, Mihail >> + >> +long long longval1; >> +long long unsigned longval2; >> + >> +long long int >> +asrl_imm () >> +{ >> + return (longval1 >> 14); >> +} >> + >> +long long unsigned int >> +lsrl_imm () >> +{ >> + return (longval2 >> 14); >> +} >> + >> +long long int >> +lsll_imm (long long int longval3) >> +{ >> + return (longval3 << 14); >> +} >> + >> +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */ >> +/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */ >> +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */ >> ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-01-20 18:05 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2019-11-14 14:19 [PATCH, GCC/ARM, 0/2] Add support for Armv8.1-M Mainline scalar shifts Mihail Ionescu
2019-11-14 14:19 ` [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M Mainline Mihail Ionescu
2019-11-14 14:25 ` [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) " Mihail Ionescu
[not found] ` <bf86297a-b750-4593-a235-c10c1510b176@VE1EUR03FT054.eop-EUR03.prod.protection.outlook.com>
2019-12-11 17:51 ` [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) " Kyrill Tkachov
2019-12-18 13:26 ` Mihail Ionescu
2020-01-17 11:21 ` Kyrill Tkachov
[not found] ` <1066f99d-b2cf-4a6a-bc55-6ba86fc88220@DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com>
2019-12-11 17:54 ` [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) " Kyrill Tkachov
[not found] ` <5dcd627a.1c69fb81.97b2a.8f10SMTPIN_ADDED_MISSING@mx.google.com>
2020-01-20 13:24 ` [PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) " Christophe Lyon
[not found] ` <5dcd628a.1c69fb81.4a132.905dSMTPIN_ADDED_MISSING@mx.google.com>
2020-01-20 13:25 ` [PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) " Christophe Lyon
2020-01-20 19:37 ` Mihail Ionescu
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