Re: Re: [PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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>> Yeah, I am aggree with you. Memory system access should always at least 1-byte.

>> So, consider such following code:

>> vsetvl e8,mf8 
>> vlm.v v8, a0 (v8 is a 1-bit mask (Not sure what the behavior dealing with this case))
>> vsm.v v8,a1
>> vsetvl e8,m1
>> vlm.v v8, a0  (v8 is a 8-bit mask)
>> vsm.v v8,a2
>> (Note: both vlm.v are loading same address)

>> Such asm will not happen in GCC. It will become like this since bool modes are tied:

>> vsetvl e8,mf8 
>> vlm.v v8, a0  (v8 is a 8-bit mask)
>> vsm.v v8,a0
>> vsm.v v8,a1

>> I am not sure whether it's correct. Maybe I should ask RVV ISA community.

Such case may not be appropriate to talke about. Since 1bit mask for VNx1BI is the minimum value.
Since the size is a poly value (1,1). It can be only be 1 bit or 1bytes or 2bytes...etc. It's a compile-time unknown which is denpending on CPU vector length.
This case should be represent as this:

vsetvl e8,mf8 
vlm.v v8, a0 (v8 is a N x 1-bit mask, N is compile-time unknown))
vsm.v v8,a1
vsetvl e8,m1
vlm.v v8, a0  (v8 is a N x 8-bit mask, N is compile-time unknown)
vsm.v v8,a2
(Note: both vlm.v are loading same address)

Such asm will not happen in GCC. It will become like this since bool modes are tied:

vsetvl e8,mf8 
vlm.v v8, a0 (v8 is a N x 1-bit mask, N is compile-time unknown))
vsm.v v8,a0
vsm.v v8,a1

Such asm codegen is incorrect, this is what we want to fix.



juzhe.zhong@rivai.ai
 
From: juzhe.zhong@rivai.ai
Date: 2023-02-13 18:28
To: richard.sandiford
CC: rguenther; incarnation.p.lee; gcc-patches; Kito.cheng; ams
Subject: Re: Re: [PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types
Yeah, I am aggree with you. Memory system access should always at least 1-byte.

So, consider such following code:

vsetvl e8,mf8 
vlm.v v8, a0 (v8 is a 1-bit mask (Not sure what the behavior dealing with this case))
vsm.v v8,a1
vsetvl e8,m1
vlm.v v8, a0  (v8 is a 8-bit mask)
vsm.v v8,a2
(Note: both vlm.v are loading same address)

Such asm will not happen in GCC. It will become like this since bool modes are tied:

vsetvl e8,mf8 
vlm.v v8, a0  (v8 is a 8-bit mask)
vsm.v v8,a0
vsm.v v8,a1

I am not sure whether it's correct. Maybe I should ask RVV ISA community.



juzhe.zhong@rivai.ai
 
From: Richard Sandiford
Date: 2023-02-13 18:18
To: juzhe.zhong\@rivai.ai
CC: rguenther; incarnation.p.lee; gcc-patches; Kito.cheng; ams
Subject: Re: [PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types
"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai> writes:
>>> What's the byte size of VNx1BI, expressed as a function of N?
>>> If it's CEIL (N, 8) then we don't have a way of representing that yet.
> N is a poly value.
> RVV like SVE support scalable vector.
> the N is poly (1,1).
>
> VNx1B mode nunits = poly(1,1) units.
> VNx1B mode bitsize =poly (1,1) bitsize.
> VNx1B mode bytesize = poly(1,1) units (currently). Ideally and more accurate, it should be VNx1B mode bytesize =poly (1/8,1/8).
 
But this would be a fractional bytesize, and like Richard says,
the memory subsystem would always access full bytes.  So I think
the bytesize would have to be at least CEIL (N, 8).
 
> However, it can't represent it like this. GCC consider its bytesize as  poly (1,1) bytesize.
 
Ah, OK.  That (making the size N bytes) does seem like a reasonable
workaround, provided that it matches the C types, etc.  So the total
amount of padding is 7N bits (I assume at the msb of the type when
viewed as an integer).
 
I agree that what (IIUC) was discussed upthread works, i.e.:
 
  bytesize = N
  bitsize = N * 8 (fixed function of bytesize)
  precision = N
  nunits = N
  unit_size = 1
  unit_precision = 1
 
But target-independent code won't expect this layout, so supporting
it will involve more than just adjusting the parameters.
 
Thanks,
Richard