commit 864d03bba8274e1281142e389961b499d6cbf81b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Feb 7 15:46:48 2018 +0000

    [i386] Make QImode subregs of zero_extracts more robust

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3998053..c5a7d88 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1328,12 +1328,12 @@ (define_insn "*cmp<mode>_minus_1"
   [(set_attr "type" "icmp")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*cmpqi_ext_1"
+(define_insn "*cmpqi<mode>_ext_1"
   [(set (reg FLAGS_REG)
 	(compare
 	  (match_operand:QI 0 "nonimmediate_operand" "QBc,m")
 	  (subreg:QI
-	    (zero_extract:SI
+	    (zero_extract:SWI248
 	      (match_operand 1 "ext_register_operand" "Q,Q")
 	      (const_int 8)
 	      (const_int 8)) 0)))]
@@ -1343,11 +1343,11 @@ (define_insn "*cmpqi_ext_1"
    (set_attr "type" "icmp")
    (set_attr "mode" "QI")])
 
-(define_insn "*cmpqi_ext_2"
+(define_insn "*cmpqi<mode>_ext_2"
   [(set (reg FLAGS_REG)
 	(compare
 	  (subreg:QI
-	    (zero_extract:SI
+	    (zero_extract:SWI248
 	      (match_operand 0 "ext_register_operand" "Q")
 	      (const_int 8)
 	      (const_int 8)) 0)
@@ -1368,11 +1368,11 @@ (define_expand "cmpqi_ext_3"
 	      (const_int 8)) 0)
 	  (match_operand:QI 1 "const_int_operand")))])
 
-(define_insn "*cmpqi_ext_3"
+(define_insn "*cmpqi<mode>_ext_3"
   [(set (reg FLAGS_REG)
 	(compare
 	  (subreg:QI
-	    (zero_extract:SI
+	    (zero_extract:SWI248
 	      (match_operand 0 "ext_register_operand" "Q,Q")
 	      (const_int 8)
 	      (const_int 8)) 0)
@@ -1383,16 +1383,16 @@ (define_insn "*cmpqi_ext_3"
    (set_attr "type" "icmp")
    (set_attr "mode" "QI")])
 
-(define_insn "*cmpqi_ext_4"
+(define_insn "*cmpqi<mode>_ext_4"
   [(set (reg FLAGS_REG)
 	(compare
 	  (subreg:QI
-	    (zero_extract:SI
+	    (zero_extract:SWI248
 	      (match_operand 0 "ext_register_operand" "Q")
 	      (const_int 8)
 	      (const_int 8)) 0)
 	  (subreg:QI
-	    (zero_extract:SI
+	    (zero_extract:SWI248
 	      (match_operand 1 "ext_register_operand" "Q")
 	      (const_int 8)
 	      (const_int 8)) 0)))]
@@ -2928,10 +2928,10 @@ (define_expand "extzv<mode>"
     operands[1] = copy_to_reg (operands[1]);
 })
 
-(define_insn "*extzvqi_mem_rex64"
+(define_insn "*extzvqi<mode>_mem_rex64"
   [(set (match_operand:QI 0 "norex_memory_operand" "=Bn")
 	(subreg:QI
-	  (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
+	  (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "Q")
 			   (const_int 8)
 			   (const_int 8)) 0))]
   "TARGET_64BIT && reload_completed"
@@ -2949,10 +2949,10 @@ (define_insn "*extzv<mode>"
   [(set_attr "type" "imovx")
    (set_attr "mode" "SI")])
 
-(define_insn "*extzvqi"
+(define_insn "*extzvqi<mode>"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
 	(subreg:QI
-	  (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q")
+	  (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "Q,Q,Q")
 			   (const_int 8)
 			   (const_int 8)) 0))]
   ""
@@ -2980,7 +2980,7 @@ (define_insn "*extzvqi"
 (define_peephole2
   [(set (match_operand:QI 0 "register_operand")
 	(subreg:QI
-	  (zero_extract:SI (match_operand 1 "ext_register_operand")
+	  (zero_extract:SWI248 (match_operand 1 "ext_register_operand")
 			   (const_int 8)
 			   (const_int 8)) 0))
    (set (match_operand:QI 2 "norex_memory_operand") (match_dup 0))]
@@ -6340,18 +6340,18 @@ (define_insn "addqi_ext_1"
 	(const_string "alu")))
    (set_attr "mode" "QI")])
 
-(define_insn "*addqi_ext_2"
+(define_insn "*addqi<mode>_ext_2"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
 			 (const_int 8)
 			 (const_int 8))
 	(subreg:SI
 	  (plus:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "%0")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "%0")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
+	      (zero_extract:SWI248 (match_operand 2 "ext_register_operand" "Q")
 			       (const_int 8)
 			       (const_int 8)) 0)) 0))
   (clobber (reg:CC FLAGS_REG))]
@@ -8596,12 +8596,12 @@ (define_expand "testqi_ext_1_ccno"
 	      (match_operand 1 "const_int_operand"))
 	  (const_int 0)))])
 
-(define_insn "*testqi_ext_1"
+(define_insn "*testqi<mode>_ext_1"
   [(set (reg FLAGS_REG)
 	(compare
 	  (and:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 0 "ext_register_operand" "Q,Q")
+	      (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "Q,Q")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (match_operand:QI 1 "general_operand" "QnBc,m"))
@@ -8612,16 +8612,16 @@ (define_insn "*testqi_ext_1"
    (set_attr "type" "test")
    (set_attr "mode" "QI")])
 
-(define_insn "*testqi_ext_2"
+(define_insn "*testqi<mode>_ext_2"
   [(set (reg FLAGS_REG)
 	(compare
 	  (and:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 0 "ext_register_operand" "Q")
+	      (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "Q")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "Q")
 			       (const_int 8)
 			       (const_int 8)) 0))
 	  (const_int 0)))]
@@ -9147,12 +9147,12 @@ (define_insn "andqi_ext_1"
 
 ;; Generated by peephole translating test to and.  This shows up
 ;; often in fp comparisons.
-(define_insn "*andqi_ext_1_cc"
+(define_insn "*andqi<mode>_ext_1_cc"
   [(set (reg FLAGS_REG)
 	(compare
 	  (and:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (match_operand:QI 2 "general_operand" "QnBc,m"))
@@ -9163,7 +9163,7 @@ (define_insn "*andqi_ext_1_cc"
 	(subreg:SI
 	  (and:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_dup 1)
+	      (zero_extract:SWI248 (match_dup 1)
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (match_dup 2)) 0))]
@@ -9175,18 +9175,18 @@ (define_insn "*andqi_ext_1_cc"
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
-(define_insn "*andqi_ext_2"
+(define_insn "*andqi<mode>_ext_2"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
 			 (const_int 8)
 			 (const_int 8))
 	(subreg:SI
 	  (and:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "%0")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "%0")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
+	      (zero_extract:SWI248 (match_operand 2 "ext_register_operand" "Q")
 			       (const_int 8)
 			       (const_int 8)) 0)) 0))
    (clobber (reg:CC FLAGS_REG))]
@@ -9564,14 +9564,14 @@ (define_insn "*<code><mode>_3"
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*<code>qi_ext_1"
+(define_insn "*<code>qi<mode>_ext_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q,Q")
 			 (const_int 8)
 			 (const_int 8))
 	(subreg:SI
 	  (any_or:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
@@ -9584,18 +9584,18 @@ (define_insn "*<code>qi_ext_1"
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
-(define_insn "*<code>qi_ext_2"
+(define_insn "*<code>qi<mode>_ext_2"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
 			 (const_int 8)
 			 (const_int 8))
 	(subreg:SI
 	  (any_or:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "%0")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "%0")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
+	      (zero_extract:SWI248 (match_operand 2 "ext_register_operand" "Q")
 			       (const_int 8)
 			       (const_int 8)) 0)) 0))
    (clobber (reg:CC FLAGS_REG))]
@@ -9681,12 +9681,12 @@ (define_expand "xorqi_ext_1_cc"
 				 (const_int 8)) 0)
 	    (match_dup 2)) 0))])])
 
-(define_insn "*xorqi_ext_1_cc"
+(define_insn "*xorqi<mode>_ext_1_cc"
   [(set (reg FLAGS_REG)
 	(compare
 	  (xor:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
+	      (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "0,0")
 			       (const_int 8)
 			       (const_int 8)) 0)
 	    (match_operand:QI 2 "general_operand" "QnBc,m"))
@@ -9697,7 +9697,7 @@ (define_insn "*xorqi_ext_1_cc"
 	(subreg:SI
 	  (xor:QI
 	    (subreg:QI
-	      (zero_extract:SI (match_dup 1)
+	      (zero_extract:SWI248 (match_dup 1)
 			       (const_int 8)
 			       (const_int 8)) 0)
 	  (match_dup 2)) 0))]
@@ -18800,7 +18800,7 @@ (define_peephole2
 	(match_operator 1 "compare_operator"
 	  [(and:QI
 	     (subreg:QI
-	       (zero_extract:SI (match_operand 2 "QIreg_operand")
+	       (zero_extract:SWI248 (match_operand 2 "QIreg_operand")
 				(const_int 8)
 				(const_int 8)) 0)
 	     (match_operand 3 "const_int_operand"))
@@ -18814,7 +18814,7 @@ (define_peephole2
 	   (match_op_dup 1
 	     [(and:QI
 		(subreg:QI
-		  (zero_extract:SI (match_dup 2)
+		  (zero_extract:SWI248 (match_dup 2)
 				   (const_int 8)
 				   (const_int 8)) 0)
 		(match_dup 3))
@@ -18825,7 +18825,7 @@ (define_peephole2
 	   (subreg:SI
 	     (and:QI
 	       (subreg:QI
-		 (zero_extract:SI (match_dup 2)
+		 (zero_extract:SWI248 (match_dup 2)
 				  (const_int 8)
 				  (const_int 8)) 0)
 	       (match_dup 3)) 0))])])