From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 37895 invoked by alias); 26 Sep 2018 11:20:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 37867 invoked by uid 89); 26 Sep 2018 11:20:19 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=June, H*u:31.0, H*UA:31.0 X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Sep 2018 11:20:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7603DED1; Wed, 26 Sep 2018 04:20:07 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E7183F5BD; Wed, 26 Sep 2018 04:20:06 -0700 (PDT) Message-ID: <5BAB6B64.2050502@foss.arm.com> Date: Wed, 26 Sep 2018 12:05:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Zhangshaokun , James Greenhalgh CC: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Richard Earnshaw , "zbo.zhou@hisilicon.com" , nd@arm.com Subject: Re: [PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support References: <1537350832-11076-1-git-send-email-zhangshaokun@hisilicon.com> <20180920142235.GA31720@arm.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2018-09/txt/msg01535.txt.bz2 Hi Shaokun, On 25/09/18 14:40, Zhangshaokun wrote: > Hi ARM maintainers, > > Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC? > I saw it has been supported in linux mainline(on Mar 7), > Patch link: > http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/565090.html > Kernel link: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/kernel/cpufeature.c?h=v4.19-rc5 +205 Do you mean implementing the data cache clearing elision in __clear_cache as discussed in June [1]? I am not aware of any plans to implement that support yet as we'd need hardware to test this properly on. If you can implement and test it and post it to the list I'm sure the maintainers would be happy to review such patches though. Thanks, Kyrill [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00307.html > Thanks, > Shaokun > > On 2018/9/20 22:22, James Greenhalgh wrote: >> On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote: >>> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A. >>> It has been tested on aarch64 and no regressions from this patch. >> This patch is OK for Trunk. >> >> Do you need someone to commit it on your behalf? >> >> Thanks, >> James >> >>> --- >>> gcc/ChangeLog | 9 +++ >>> gcc/config/aarch64/aarch64-cores.def | 3 + >>> gcc/config/aarch64/aarch64-cost-tables.h | 104 +++++++++++++++++++++++++++++++ >>> gcc/config/aarch64/aarch64-tune.md | 2 +- >>> gcc/config/aarch64/aarch64.c | 82 ++++++++++++++++++++++++ >>> gcc/doc/invoke.texi | 2 +- >>> 6 files changed, 200 insertions(+), 2 deletions(-) >>> >>> diff --git a/gcc/ChangeLog b/gcc/ChangeLog >>> index 69e2e14..a040daa 100644 >>> --- a/gcc/ChangeLog >>> +++ b/gcc/ChangeLog >>> @@ -1,3 +1,12 @@ >>> +2018-09-19 Shaokun Zhang >>> + Bo Zhou >>> + >>> + * config/aarch64/aarch64-cores.def (tsv110): New CPU. >>> + * config/aarch64/aarch64-tune.md: Regenerated. >>> + * doc/invoke.texi (AArch64 Options/-mtune): Add "tsv110". >>> + * config/aarch64/aarch64.c (tsv110_tunings): New tuning table. >>> + * config/aarch64/aarch64-cost-tables.h: Add "tsv110" extra costs. >>> + >>> 2018-09-18 Marek Polacek >>> >>> P1064R0 - Allowing Virtual Function Calls in Constant Expressions >> >> >> . >>