[PATCH][GCC][Arm] Fix arm big-endian intrinsics regressions.

[PATCH][GCC][Arm] Fix arm big-endian intrinsics regressions.

[Tamar Christina]

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Hi All,

We are a bit inconsistent when it comes to lane index endianness on Arm,
we don't seem to always stick to the expected GCC vector extensions index
endianness, for these tests since they are modelled as UNSPEC anyway just
keep the indexes in Arm NEON order.

There are other intrinsics that require an update, but for now these will
fix the new ones.

Bootstrapped Regtested on arm-none-Linux-gnueabihf and no issues.
Cross compiled on armeb-none-eabi and regtested and no issues.
Verified example by hand with execution tests and no issues.

Ok for trunk?

Thanks,
Tamar

gcc/ChangeLog:

2019-01-15  Tamar Christina  <tamar.christina@arm.com>

	* config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): Remove patternmode.
	* config/arm/arm.c (neon_vcmla_lane_prepare_operands): Likewise.
	* config/arm/neon.md (neon_vcmla_lane<rot><mode>, neon_vcmla_laneq<rot><mode>,
	neon_vcmlaq_lane<rot><mode>): Remove endianness conversion.

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diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 2bc43019864ef70ed1bf1e725bad7437cf9b11d8..79ede0db174fcce87abe8b4d18893550d4c7e2f6 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -109,7 +109,7 @@ extern int arm_coproc_mem_operand (rtx, bool);
 extern int neon_vector_mem_operand (rtx, int, bool);
 extern int neon_struct_mem_operand (rtx);
 
-extern rtx *neon_vcmla_lane_prepare_operands (machine_mode, rtx *);
+extern rtx *neon_vcmla_lane_prepare_operands (rtx *);
 
 extern int tls_mentioned_p (rtx);
 extern int symbol_mentioned_p (rtx);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index cb5e7215e813dc922d606662df3fdc5040fd3524..0b598d20a46ebc6b5c29c782228da045f9a078c1 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12724,8 +12724,7 @@ neon_struct_mem_operand (rtx op)
 /* Prepares the operands for the VCMLA by lane instruction such that the right
    register number is selected.  This instruction is special in that it always
    requires a D register, however there is a choice to be made between Dn[0],
-   Dn[1], D(n+1)[0], and D(n+1)[1] depending on the mode of the registers and
-   the PATTERNMODE of the insn.
+   Dn[1], D(n+1)[0], and D(n+1)[1] depending on the mode of the registers.
 
    The VCMLA by lane function always selects two values. For instance given D0
    and a V2SF, the only valid index is 0 as the values in S0 and S1 will be
@@ -12737,9 +12736,9 @@ neon_struct_mem_operand (rtx op)
    updated to contain the right index.  */
 
 rtx *
-neon_vcmla_lane_prepare_operands (machine_mode patternmode, rtx *operands)
+neon_vcmla_lane_prepare_operands (rtx *operands)
 {
-  int lane = NEON_ENDIAN_LANE_N (patternmode, INTVAL (operands[4]));
+  int lane = INTVAL (operands[4]);
   machine_mode constmode = SImode;
   machine_mode mode = GET_MODE (operands[3]);
   int regno = REGNO (operands[3]);
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 6f8e7c1cffd2751c1ee7e03ded0410ad3c09c13f..f9d7ba35b137fed383f84eecbe81dd942943d216 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -3494,7 +3494,7 @@
 			     VCMLA)))]
   "TARGET_COMPLEX"
   {
-    operands = neon_vcmla_lane_prepare_operands (<MODE>mode, operands);
+    operands = neon_vcmla_lane_prepare_operands (operands);
     return "vcmla.<V_s_elem>\t%<V_reg>0, %<V_reg>2, d%c3[%c4], #<rot>";
   }
   [(set_attr "type" "neon_fcmla")]
@@ -3509,7 +3509,7 @@
 			      VCMLA)))]
   "TARGET_COMPLEX"
   {
-    operands = neon_vcmla_lane_prepare_operands (<MODE>mode, operands);
+    operands = neon_vcmla_lane_prepare_operands (operands);
     return "vcmla.<V_s_elem>\t%<V_reg>0, %<V_reg>2, d%c3[%c4], #<rot>";
   }
   [(set_attr "type" "neon_fcmla")]
@@ -3524,7 +3524,7 @@
 				 VCMLA)))]
   "TARGET_COMPLEX"
   {
-    operands = neon_vcmla_lane_prepare_operands (<MODE>mode, operands);
+    operands = neon_vcmla_lane_prepare_operands (operands);
     return "vcmla.<V_s_elem>\t%<V_reg>0, %<V_reg>2, d%c3[%c4], #<rot>";
   }
   [(set_attr "type" "neon_fcmla")]

Re: [PATCH][GCC][Arm] Fix arm big-endian intrinsics regressions.

[Kyrill Tkachov]

Hi Tamar,

On 15/01/19 17:05, Tamar Christina wrote:
> Hi All,
>
> We are a bit inconsistent when it comes to lane index endianness on Arm,
> we don't seem to always stick to the expected GCC vector extensions index
> endianness, for these tests since they are modelled as UNSPEC anyway just
> keep the indexes in Arm NEON order.
>
> There are other intrinsics that require an update, but for now these will
> fix the new ones.
>
> Bootstrapped Regtested on arm-none-Linux-gnueabihf and no issues.
> Cross compiled on armeb-none-eabi and regtested and no issues.
> Verified example by hand with execution tests and no issues.
>
> Ok for trunk?
>

Ok.
We should aim to make the lane-flipping consistent in the future.

Thanks,
Kyrill

> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> 2019-01-15  Tamar Christina  <tamar.christina@arm.com>
>
>         * config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): Remove patternmode.
>         * config/arm/arm.c (neon_vcmla_lane_prepare_operands): Likewise.
>         * config/arm/neon.md (neon_vcmla_lane<rot><mode>, neon_vcmla_laneq<rot><mode>,
>         neon_vcmlaq_lane<rot><mode>): Remove endianness conversion.
>
> --