From: Jeff Law <jeffreyalaw@gmail.com>
To: Xiongchuan Tan <xc-tan@outlook.com>, gcc-patches@gcc.gnu.org
Cc: fantasquex@gmail.com, andrew@sifive.com
Subject: Re: [PATCH v2] RISC-V: Libitm add RISC-V support.
Date: Thu, 27 Oct 2022 17:05:19 -0600 [thread overview]
Message-ID: <5ac3d38a-27c1-cc4a-dc4b-9d82e109503a@gmail.com> (raw)
In-Reply-To: <OSYP286MB0261ABB716605DE32EC2C58B91339@OSYP286MB0261.JPNP286.PROD.OUTLOOK.COM>
On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote:
> libitm/ChangeLog:
>
> * configure.tgt: Add riscv support.
> * config/riscv/asm.h: New file.
> * config/riscv/sjlj.S: New file.
> * config/riscv/target.h: New file.
> ---
> v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)
>
> libitm/config/riscv/asm.h | 52 +++++++++++++
> libitm/config/riscv/sjlj.S | 144 +++++++++++++++++++++++++++++++++++
> libitm/config/riscv/target.h | 50 ++++++++++++
> libitm/configure.tgt | 2 +
> 4 files changed, 248 insertions(+)
> create mode 100644 libitm/config/riscv/asm.h
> create mode 100644 libitm/config/riscv/sjlj.S
> create mode 100644 libitm/config/riscv/target.h
Not objecting or even reviewing.... But hasn't transactional memory
largely fallen out of favor these days? Intel has pulled it and I think
IBM did as well. Should we be investing in extending libitm at all?
jeff
next prev parent reply other threads:[~2022-10-27 23:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-27 12:49 Xiongchuan Tan
2022-10-27 23:05 ` Jeff Law [this message]
2022-10-28 0:44 ` Palmer Dabbelt
2022-10-28 4:23 ` Xi Ruoyao
2022-10-29 3:18 ` Jeff Law
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