From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from omggw0021-vm1.mail.otm.yahoo.co.jp (omggw0021-vm1.mail.otm.yahoo.co.jp [182.22.19.59]) by sourceware.org (Postfix) with ESMTPS id F191F3858D35 for ; Tue, 23 May 2023 05:48:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F191F3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=yahoo.co.jp Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=yahoo.co.jp X-YMail-OSG: s.5XJPkVM1knECFVL7gIRvgOKvPJ0YO7B2tj7UwCRdXMJaKtiJoYVSdZjA1_nhz j4RGeQABWbp_jFl0fcQdF7e5O_tF198E10gIGleeI_UFW7TtkyoV2DFJdbuy5I45BQe9M.Hue5xu J54yPTs6R5R2voz4eR4SSU2zL8OPgUNeRzGevHDMkdyJOHZAMgMwRlTbDuDJUqNgy1006fb1kW2Z IsuYZmq5lYkuw_0D6T__DBBOMyZxoIx3SQ4w79kDSEuK87RHPFQjnz2tqHHKlY_HARYJU.heKe0f km.R5Mv9nuddmkPZHEy36iI8YaB7MxtRuHaJHQNMdd7qblLB3VHH.HmWzFu_kCpZZBQ7hZ99TYPi CnCL7ZF_cPJcy8SQjZgKLH.jvwz5_s2iwajCWkZUCw.3xxi_jpFWW6wullFNRJm8FUuyrcQo1Xci _rYitd_gHyEssTSF9iM49oxJcCWznGEdyrgbTNyqYa8ZGhKxYvbxj_AA2sKjBdpcWen5Us5joOe. ix54gm1zvOtOLHf_Ik6A8Xx1VAL2aoY2Y9wejUY.FYffeI2wmwKGEXGnT43_YcFbdUQURD2hQOCe dmBlAyMMXBCRoA4FjpOlcJKCZ4f.EDm46GmB4ARBiC9o7X_oQncHV7W9HboVAnRzbmZpjkG5GFMz WuquU1GhPmBAy7ruF6zhTEYpwFbjN9iTnqFbo6VoBZRL5ZToZLs45ulM9l_tTQnuGlPLrrq4mHXL SHKxeZcBhgtYJ1HbRpxDU5gf5IZDjrOuM8mVlfOiNQdWf6QRSOTwf.EX2UJY4s8wIEqQbNbthmYf WhzaMBeLsuSXhu9qTE2on1HA6PBxAwtU8OVPRnc5WWuNjmkkoeZpMfPStxwhb8TRBG2J7H1fTYQ4 g.e0rIlEA2co1K3JKNxr6YRa7GJiIfPQ.XJYt6u3VrgLX0rqwzU4NlmaiVYaZUxOfAiC8BaGNgCB uHI81VEISVBy_91LjUPPBBQVhRzgFNTjvVufGLf7J_vSMtxxuwcEXiIT0IjaRNDQ1fJY- Received: from sonicgw.mail.yahoo.co.jp by sonicconh6003.mail.ssk.yahoo.co.jp with HTTP; Tue, 23 May 2023 05:48:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1684820893; s=yj20110701; d=yahoo.co.jp; h=Message-ID:Date:MIME-Version:Subject:To:References:Cc:From:In-Reply-To:Content-Type:Content-Transfer-Encoding; bh=54GCt4+BWuEoie2a91sM6tpbPvu3Q7NTNzocGBjw+RA=; b=dH2R1xx5CV/OI2eJx9pSSWuDq/eMqX+JPZIjznbF/v7L2g7ySPZh/pSU9ZiN4N9V peeSB8xO/Q9jsVOzXS1mlnO9STaENvw9cFFovU3aNqqSFLpTHp2CX2zfYzDU9yxjYRH FOb1egqn6wGmqkpAxRIvAgh35j+4CR7U50r5ewg4= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=yj20110701; d=yahoo.co.jp; h=Message-ID:Date:MIME-Version:References:Cc:From:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=FLjYwVtC1wnvJZ24+qMn8qWE3VDYmC0ACgGmyRZMhNofn0m5ECgs9sH8A0ESR4GF 6vNIAI2IFT5+zXdEHJTHgTjG9weTvFre39idizECQ2rjynBo2n/2Z9pwQClQfiRbcRH t3VnOddJgAst+1X1TsMD9hVVU89b9RgPgB+R6ZXg=; Received: by smtphe5002.mail.kks.ynwp.yahoo.co.jp (YJ Hermes SMTP Server) with ESMTPA ID a1e25c42628361b5d8fd6945209ad074; Tue, 23 May 2023 14:48:09 +0900 (JST) Message-ID: <5b04c828-7906-2efb-a834-d3ed0ba1f6bd@yahoo.co.jp> Date: Tue, 23 May 2023 14:48:09 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: [PATCH v2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' To: GCC Patches References: Cc: Max Filippov From: Takayuki 'January June' Suwa In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,GIT_PATCH_0,KAM_DMARC_STATUS,NML_ADSP_CUSTOM_MED,PLING_QUERY,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2023/05/23 11:27, Max Filippov wrote: > Hi Suwa-san, Hi! > This change introduces a bunch of test failures on big endian configuration. > I believe that's because the starting bit position for zero_extract is counted > from different ends depending on the endianness. Oops, what a stupid mistake... X( === This patch decreses one machine instruction from "single bit extraction with shifting" operation, and tries to eliminate the conditional branch if CST2_POW2 doesn't fit into signed 12 bits with the help of ifcvt optimization. /* example #1 */ int test0(int x) { return (x & 1048576) != 0 ? 1024 : 0; } extern int foo(void); int test1(void) { return (foo() & 1048576) != 0 ? 16777216 : 0; } ;; before test0: movi a9, 0x400 srai a2, a2, 10 and a2, a2, a9 ret.n test1: addi sp, sp, -16 s32i.n a0, sp, 12 call0 foo extui a2, a2, 20, 1 slli a2, a2, 20 beqz.n a2, .L2 movi.n a2, 1 slli a2, a2, 24 .L2: l32i.n a0, sp, 12 addi sp, sp, 16 ret.n ;; after test0: extui a2, a2, 20, 1 slli a2, a2, 10 ret.n test1: addi sp, sp, -16 s32i.n a0, sp, 12 call0 foo l32i.n a0, sp, 12 extui a2, a2, 20, 1 slli a2, a2, 24 addi sp, sp, 16 ret.n In addition, if the left shift amount ('exact_log2(CST2_POW2)') is between 1 through 3 and a either addition or subtraction with another register follows, emit a ADDX[248] or SUBX[248] machine instruction instead of separate left shift and add/subtract ones. /* example #2 */ int test2(int x, int y) { return ((x & 1048576) != 0 ? 4 : 0) + y; } int test3(int x, int y) { return ((x & 2) != 0 ? 8 : 0) - y; } ;; before test2: movi.n a9, 4 srai a2, a2, 18 and a2, a2, a9 add.n a2, a2, a3 ret.n test3: movi.n a9, 8 slli a2, a2, 2 and a2, a2, a9 sub a2, a2, a3 ret.n ;; after test2: extui a2, a2, 20, 1 addx4 a2, a2, a3 ret.n test3: extui a2, a2, 1, 1 subx8 a2, a2, a3 ret.n gcc/ChangeLog: * config/xtensa/predicates.md (addsub_operator): New. * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3, *extzvsi-1bit_addsubx): New insn_and_split patterns. * config/xtensa/xtensa.cc (xtensa_rtx_costs): Add a special case about ifcvt 'noce_try_cmove()' to handle constant loads that do not fit into signed 12 bits in the patterns added above. --- gcc/config/xtensa/predicates.md | 3 ++ gcc/config/xtensa/xtensa.cc | 3 +- gcc/config/xtensa/xtensa.md | 83 +++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+), 1 deletion(-) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index 2dac193373a..5faf1be8c15 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -191,6 +191,9 @@ (define_predicate "logical_shift_operator" (match_code "ashift,lshiftrt")) +(define_predicate "addsub_operator" + (match_code "plus,minus")) + (define_predicate "xtensa_cstoresi_operator" (match_code "eq,ne,gt,ge,lt,le")) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index bb1444c44b6..e3af78cd228 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -4355,7 +4355,8 @@ xtensa_rtx_costs (rtx x, machine_mode mode, int outer_code, switch (outer_code) { case SET: - if (xtensa_simm12b (INTVAL (x))) + if (xtensa_simm12b (INTVAL (x)) + || (current_pass && current_pass->tv_id == TV_IFCVT)) { *total = speed ? COSTS_N_INSNS (1) : 0; return true; diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 3521fa33b47..c75fde1023a 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -997,6 +997,89 @@ (set_attr "mode" "SI") (set_attr "length" "3")]) +(define_insn_and_split "*extzvsi-1bit_ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")]) + (match_operand:SI 3 "const_int_operand" "i")))] + "exact_log2 (INTVAL (operands[3])) > 0" + "#" + "&& 1" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (const_int 1) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 3)))] +{ + int pos = INTVAL (operands[2]), + shift = floor_log2 (INTVAL (operands[3])); + switch (GET_CODE (operands[4])) + { + case ASHIFT: + pos = shift - pos; + break; + case LSHIFTRT: + pos = shift + pos; + break; + default: + gcc_unreachable (); + } + if (BITS_BIG_ENDIAN) + pos = (32 - (1 + pos)) & 0x1f; + operands[2] = GEN_INT (pos); + operands[3] = GEN_INT (shift); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*extzvsi-1bit_addsubx" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 5 "addsub_operator" + [(and:SI (match_operator:SI 6 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 3 "const_int_operand" "i")]) + (match_operand:SI 4 "const_int_operand" "i")) + (match_operand:SI 2 "register_operand" "r")]))] + "TARGET_ADDX + && IN_RANGE (exact_log2 (INTVAL (operands[4])), 1, 3)" + "#" + "&& 1" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (const_int 1) + (match_dup 3))) + (set (match_dup 0) + (match_op_dup 5 + [(ashift:SI (match_dup 0) + (match_dup 4)) + (match_dup 2)]))] +{ + int pos = INTVAL (operands[3]), + shift = floor_log2 (INTVAL (operands[4])); + switch (GET_CODE (operands[6])) + { + case ASHIFT: + pos = shift - pos; + break; + case LSHIFTRT: + pos = shift + pos; + break; + default: + gcc_unreachable (); + } + if (BITS_BIG_ENDIAN) + pos = (32 - (1 + pos)) & 0x1f; + operands[3] = GEN_INT (pos); + operands[4] = GEN_INT (shift); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + ;; Conversions. -- 2.30.2