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From: Richard Henderson <richard.henderson@linaro.org>
To: Wilco Dijkstra <Wilco.Dijkstra@arm.com>,
	GCC Patches <gcc-patches@gcc.gnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
Cc: nd <nd@arm.com>,
	Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com>,
	"agraf@suse.de" <agraf@suse.de>,
	Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
	James Greenhalgh <James.Greenhalgh@arm.com>
Subject: Re: [PATCH, AArch64, v3 0/6] LSE atomics out-of-line
Date: Sat, 14 Sep 2019 19:26:00 -0000	[thread overview]
Message-ID: <5c4cbe49-8613-b9e4-9011-df26ced40a35@linaro.org> (raw)
In-Reply-To: <VI1PR0801MB212764F895C50D4A51E7748183BB0@VI1PR0801MB2127.eurprd08.prod.outlook.com>

On 9/5/19 10:35 AM, Wilco Dijkstra wrote:
> Agreed. I've got a couple of general comments:
> 
> * The option name -matomic-ool sounds too abbreviated. I think eg.
> -moutline-atomics is more descriptive and user friendlier.

Changed.

> * Similarly the exported __aa64_have_atomics variable could be named
>   __aarch64_have_lse_atomics so it's clear that it is about LSE atomics.

Changed.

> +@item -matomic-ool
> +@itemx -mno-atomic-ool
> +Enable or disable calls to out-of-line helpers to implement atomic operations.
> +These helpers will, at runtime, determine if ARMv8.1-Atomics instructions
> +should be used; if not, they will use the load/store-exclusive instructions
> +that are present in the base ARMv8.0 ISA.
> +
> +This option is only applicable when compiling for the base ARMv8.0
> +instruction set.  If using a later revision, e.g. @option{-march=armv8.1-a}
> +or @option{-march=armv8-a+lse}, the ARMv8.1-Atomics instructions will be
> +used directly. 
> 
> So what is the behaviour when you explicitly select a specific CPU?

Selecting a specific cpu selects the specific architecture that the cpu
supports, does it not?  Thus the architecture example above still applies.

Unless I don't understand what distinction that you're making?

> +/* Branch to LABEL if LSE is enabled.
> +   The branch should be easily predicted, in that it will, after constructors,
> +   always branch the same way.  The expectation is that systems that implement
> +   ARMv8.1-Atomics are "beefier" than those that omit the extension.
> +   By arranging for the fall-through path to use load-store-exclusive insns,
> +   we aid the branch predictor of the smallest cpus.  */ 
> 
> I'd say that by the time GCC10 is released and used in distros, systems without
> LSE atomics would be practically non-existent. So we should favour LSE atomics
> by default.

I suppose.  Does it not continue to be true that an a53 is more impacted by the
branch prediction than an a76?


r~

  reply	other threads:[~2019-09-14 19:26 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-05 14:36 Wilco Dijkstra
2019-09-14 19:26 ` Richard Henderson [this message]
2019-09-16 11:59   ` Wilco Dijkstra
2019-09-17  8:40     ` Kyrill Tkachov
2019-09-17 10:55       ` Wilco Dijkstra
2019-09-17 21:11         ` Richard Henderson
  -- strict thread matches above, loose matches on Subject: below --
2018-11-01 21:47 Richard Henderson
2018-11-11 12:30 ` Richard Henderson
2019-09-05  9:51 ` Kyrill Tkachov

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