From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id 6D1FD3857826 for ; Tue, 11 Oct 2022 11:02:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6D1FD3857826 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.95,176,1661846400"; d="scan'208";a="87280554" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 11 Oct 2022 03:02:36 -0800 IronPort-SDR: 6dBJNlvrg1F6bIF7VkHDphnB8lY2ry55oJZH1Ho3jNj6zjnxxdGBYnS6OhWmx0J1GA+eEOjwPn NkSIw7UN4H89dYzNIZRhx6DVpEVn3BBFWCE4BnZF1d3oAHplQmq50EdmvqzzPVMKFzRUlLOLzw QzCVyXtVJElgNnl/dEY/HBWoI4Zf0dkq47pRYoXtzPj/Z8NYZOCw5kYwvTKVTiTigdmM2JmgCd AW7crqGzaXj36ktZtanHnDBL1eA1Cr46jq9GeWirQsm5kEoBNqrar3gV2SKESuSTyvoVVVkwEJ 2rY= From: Andrew Stubbs To: Subject: [committed 3/6] amdgcn: Add vec_extract for partial vectors Date: Tue, 11 Oct 2022 12:02:05 +0100 Message-ID: <5cfe08555034b29f301dcfb99a3691c81b2e2def.1665485382.git.ams@codesourcery.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.37.0" Content-Transfer-Encoding: 8bit X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-14.mgc.mentorg.com (139.181.222.14) To svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --------------2.37.0 Content-Type: text/plain; charset="UTF-8"; format=fixed Content-Transfer-Encoding: 8bit Add vec_extract expanders for all valid pairs of vector types. gcc/ChangeLog: * config/gcn/gcn-protos.h (get_exec): Add prototypes for two variants. * config/gcn/gcn-valu.md (vec_extract): New define_expand. * config/gcn/gcn.cc (get_exec): Export the existing function. Add a new overload variant. --- gcc/config/gcn/gcn-protos.h | 2 ++ gcc/config/gcn/gcn-valu.md | 34 ++++++++++++++++++++++++++++++++++ gcc/config/gcn/gcn.cc | 9 ++++++++- 3 files changed, 44 insertions(+), 1 deletion(-) --------------2.37.0 Content-Type: text/x-patch; name="0003-amdgcn-Add-vec_extract-for-partial-vectors.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="0003-amdgcn-Add-vec_extract-for-partial-vectors.patch" diff --git a/gcc/config/gcn/gcn-protos.h b/gcc/config/gcn/gcn-protos.h index 6300c1cbd36..f9a1fc00b4f 100644 --- a/gcc/config/gcn/gcn-protos.h +++ b/gcc/config/gcn/gcn-protos.h @@ -24,6 +24,8 @@ extern bool gcn_constant64_p (rtx); extern bool gcn_constant_p (rtx); extern rtx gcn_convert_mask_mode (rtx reg); extern unsigned int gcn_dwarf_register_number (unsigned int regno); +extern rtx get_exec (int64_t); +extern rtx get_exec (machine_mode mode); extern char * gcn_expand_dpp_shr_insn (machine_mode, const char *, int, int); extern void gcn_expand_epilogue (); extern rtx gcn_expand_scaled_offsets (addr_space_t as, rtx base, rtx offsets, diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index c7be2361164..9ea60e1174f 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -808,6 +808,40 @@ (define_insn "vec_extract" (set_attr "exec" "none") (set_attr "laneselect" "yes")]) +(define_expand "vec_extract" + [(set (match_operand:V_ALL_ALT 0 "register_operand") + (vec_select:V_ALL_ALT + (match_operand:V_ALL 1 "register_operand") + (parallel [(match_operand 2 "immediate_operand")])))] + "MODE_VF (mode) < MODE_VF (mode) + && mode == mode" + { + int numlanes = GET_MODE_NUNITS (mode); + int firstlane = INTVAL (operands[2]) * numlanes; + rtx tmp; + + if (firstlane == 0) + { + /* A plain move will do. */ + tmp = operands[1]; + } else { + /* FIXME: optimize this by using DPP where available. */ + + rtx permutation = gen_reg_rtx (mode); + emit_insn (gen_vec_series (permutation, + GEN_INT (firstlane*4), + GEN_INT (4))); + + tmp = gen_reg_rtx (mode); + emit_insn (gen_ds_bpermute (tmp, permutation, operands[1], + get_exec (mode))); + } + + emit_move_insn (operands[0], + gen_rtx_SUBREG (mode, tmp, 0)); + DONE; + }) + (define_expand "extract_last_" [(match_operand: 0 "register_operand") (match_operand:DI 1 "gcn_alu_operand") diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index e1636f6ddd6..fdcf290ef8b 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -846,7 +846,7 @@ gcn_ira_change_pseudo_allocno_class (int regno, reg_class_t cl, /* Create a new DImode pseudo reg and emit an instruction to initialize it to VAL. */ -static rtx +rtx get_exec (int64_t val) { rtx reg = gen_reg_rtx (DImode); @@ -854,6 +854,13 @@ get_exec (int64_t val) return reg; } +rtx +get_exec (machine_mode mode) +{ + int vf = (VECTOR_MODE_P (mode) ? GET_MODE_NUNITS (mode) : 1); + return get_exec (0xffffffffffffffffUL >> (64-vf)); +} + /* }}} */ /* {{{ Immediate constants. */ --------------2.37.0--