From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id 970A93841454 for ; Tue, 7 Jun 2022 08:17:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 970A93841454 Received: from localhost.localdomain (xry111.site [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id B6689667CA; Tue, 7 Jun 2022 04:17:26 -0400 (EDT) Message-ID: <5e2a5b29aaa1243b30946af478852cda50fb226b.camel@xry111.site> Subject: Re: [PATCH] Mips: Fix the ASAN shadow offset hook for the n32 ABI From: Xi Ruoyao To: Dimitrije Milosevic , "gcc-patches@gcc.gnu.org" Cc: Djordje Todorovic Date: Tue, 07 Jun 2022 16:17:24 +0800 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.2 MIME-Version: 1.0 X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Jun 2022 08:17:33 -0000 On Mon, 2022-06-06 at 09:28 +0000, Dimitrije Milosevic wrote: > Fix the ASAN shadow offset hook for the n32 ABI. >=20 > gcc/ChangeLog: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * config/mips/mips.cc (mips_as= an_shadow_offset): Reformat > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 to handle the N32 ABI. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * config/mips/mips.h (SUBTARGE= T_SHADOW_OFFSET): Remove > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 the macro, as it is not needed= anymore. >=20 > --- >=20 > =C2=A0gcc/config/mips/mips.cc | 7 ++++++- > =C2=A0gcc/config/mips/mips.h=C2=A0 | 7 ------- > =C2=A02 files changed, 6 insertions(+), 8 deletions(-) >=20 > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc > index 2dce4007678..91e651c458e 100644 > --- a/gcc/config/mips/mips.cc > +++ b/gcc/config/mips/mips.cc > @@ -22745,7 +22745,12 @@ mips_constant_alignment (const_tree exp, > HOST_WIDE_INT align) > =C2=A0static unsigned HOST_WIDE_INT > =C2=A0mips_asan_shadow_offset (void) > =C2=A0{ > -=C2=A0 return SUBTARGET_SHADOW_OFFSET; > +=C2=A0 if (mips_abi =3D=3D ABI_N32) > +=C2=A0=C2=A0=C2=A0 return (HOST_WIDE_INT_1 << 29); > +=C2=A0 if (POINTER_SIZE =3D=3D 64) > +=C2=A0=C2=A0=C2=A0 return (HOST_WIDE_INT_1 << 37); > +=C2=A0 else > +=C2=A0=C2=A0=C2=A0 return HOST_WIDE_INT_C (0x0aaa0000); > =C2=A0} >=20 > =C2=A0/* Implement TARGET_STARTING_FRAME_OFFSET.=C2=A0 See > mips_compute_frame_info > diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h > index 858bbba3a36..0029864fdcd 100644 > --- a/gcc/config/mips/mips.h > +++ b/gcc/config/mips/mips.h > @@ -3463,10 +3463,3 @@ struct GTY(())=C2=A0 machine_function { > =C2=A0=C2=A0=C2=A0 && !TARGET_MICROMIPS && !TARGET_FIX_24K) >=20 > =C2=A0#define NEED_INDICATE_EXEC_STACK 0 > - > -/* Define the shadow offset for asan. Other OS's can override in the > -=C2=A0=C2=A0 respective tm.h files.=C2=A0 */ > -#ifndef SUBTARGET_SHADOW_OFFSET > -#define SUBTARGET_SHADOW_OFFSET \ > -=C2=A0 (POINTER_SIZE =3D=3D 64 ? HOST_WIDE_INT_1 << 37 : HOST_WIDE_INT_C > (0x0aaa0000)) > -#endif >=20 > --- I think this depends on https://reviews.llvm.org/D127096 (not committed yet)? --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University