From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 3C2F73858D1E for ; Tue, 20 Jun 2023 06:04:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C2F73858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35K5oClp006092; Tue, 20 Jun 2023 06:04:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=Nr98XrqQsbfPgPsDXaCjPm2kgoD3p899/plBHeKMj4E=; b=BaxoddPHTATlQmiAodZ7bpLZbSx4vDRwI9XN4xMlnmt0OWjEVSkL0Ds/oDfl4VpU4BeF FWXoW0dVJ1C++yBR8UQ9lMnkRzWt4KR9YHC78Wy+UYhhRQhnGak17aoBTlrcoUwj+WJI MFeYFEgTgh0YSP968xygNAW72gaA5Lm21eOgrygrCYA1opQPV4S/TeXKimlOXPd56rk2 9q3bFkKLaQJImjH1OH1aNCKQ5Vvrd+NcatHK8UVSaSsxlP+bJAgRoAIjuiRzFm9V/uDF sdaP9SWZcGdq06czMGLoMqadYFNFwZP0mvoMSMVoi7lRXY0qG8EmBz21sngm3sOXVIH1 lQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rb6am0e0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 06:04:45 +0000 Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 35K5oKL5006331; Tue, 20 Jun 2023 06:04:36 GMT Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rb6am0cv9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 06:04:36 +0000 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 35K2QPOR013325; Tue, 20 Jun 2023 06:04:22 GMT Received: from smtprelay01.fra02v.mail.ibm.com ([9.218.2.227]) by ppma04ams.nl.ibm.com (PPS) with ESMTPS id 3r94f59vj4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 06:04:21 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 35K64IUI14615068 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 20 Jun 2023 06:04:18 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9E8F720043; Tue, 20 Jun 2023 06:04:18 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A1D1F20040; Tue, 20 Jun 2023 06:04:16 +0000 (GMT) Received: from [9.197.252.125] (unknown [9.197.252.125]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 20 Jun 2023 06:04:16 +0000 (GMT) Message-ID: <5e541dcd-8907-bf59-5022-09278d82969f@linux.ibm.com> Date: Tue, 20 Jun 2023 14:04:14 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCHv3, rs6000] Add two peephole2 patterns for mr. insn Content-Language: en-US To: HAO CHEN GUI Cc: Segher Boessenkool , David , Peter Bergner , gcc-patches References: <3378371f-a40b-d582-9be5-27de60ece7bf@linux.ibm.com> From: "Kewen.Lin" In-Reply-To: <3378371f-a40b-d582-9be5-27de60ece7bf@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: CuCT5pz5SBtSsHDVbVSuzwhiwR7hoclU X-Proofpoint-GUID: qd9ktXoN9XXwagHj_Ypyttmlnagp-btz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-20_03,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306200055 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Haochen, on 2023/6/13 16:49, HAO CHEN GUI wrote: > Hi, > This patch adds two peephole2 patterns which help convert certain insn > sequences to "mr." instruction. These insn sequences can't be combined in > combine pass. > > Compared to last version, it changes the new mode iterator name from "Q" > to "WORD". > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. > > Thanks > Gui Haochen > > ChangeLog > rs6000: Add two peephole patterns for "mr." insn > > When investigating the issue mentioned in PR87871#c30 - if compare > and move pattern benefits before RA, I checked the assembly generated > for SPEC2017 and found that certain insn sequences aren't converted to > "mr." instructions. > Following two sequence are never to be combined to "mr." pattern as > there is no register link between them. This patch adds two peephole2 > patterns to convert them to "mr." instructions. > > cmp 0,3,0 > mr 4,3 > > mr 4,3 > cmp 0,3,0 > > The patch also creates a new mode iterator which decided by > TARGET_POWERPC64. This mode iterator is used in "mr." and its split > pattern. The original P iterator is wrong when -m32/-mpowerpc64 is set. > In this situation, the "mr." should compares the whole 64-bit register > with 0 other than the low 32-bit one. > > gcc/ > * config/rs6000/rs6000.md (peephole2 for compare_and_move): New. > (peephole2 for move_and_compare): New. > (mode_iterator WORD): New. Set the mode to SI/DImode by > TARGET_POWERPC64. > (*mov_internal2): Change the mode iterator from P to WORD. > (split pattern for compare_and_move): Likewise. > > gcc/testsuite/ > * gcc.dg/rtl/powerpc/move_compare_peephole_32.c: New. > * gcc.dg/rtl/powerpc/move_compare_peephole_64.c: New. > > > patch.diff > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index b0db8ae508d..1f0fe85b9b5 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -491,6 +491,7 @@ (define_mode_iterator SDI [SI DI]) > ; The size of a pointer. Also, the size of the value that a record-condition > ; (one with a '.') will compare; and the size used for arithmetic carries. > (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) > +(define_mode_iterator WORD [(SI "!TARGET_POWERPC64") (DI "TARGET_POWERPC64")]) > > ; Iterator to add PTImode along with TImode (TImode can go in VSX registers, > ; PTImode is GPR only) > @@ -7879,9 +7880,9 @@ (define_split > > (define_insn "*mov_internal2" > [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") > - (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r") > + (compare:CC (match_operand:WORD 1 "gpc_reg_operand" "0,r,r") > (const_int 0))) > - (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] > + (set (match_operand:WORD 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] > "" > "@ > cmpi %2,%0,0 > @@ -7891,11 +7892,41 @@ (define_insn "*mov_internal2" > (set_attr "dot" "yes") > (set_attr "length" "4,4,8")]) > > +(define_peephole2 > + [(set (match_operand:CC 2 "cc_reg_operand" "") > + (compare:CC (match_operand:WORD 1 "int_reg_operand" "") > + (const_int 0))) > + (set (match_operand:WORD 0 "int_reg_operand" "") > + (match_dup 1))] > + "!cc_reg_not_cr0_operand (operands[2], CCmode)" > + [(parallel [(set (match_operand:CC 2 "cc_reg_operand" "=x") > + (compare:CC (match_operand:WORD 1 "int_reg_operand" "r") > + (const_int 0))) > + (set (match_operand:WORD 0 "int_reg_operand" "=r") > + (match_dup 1))])] > + "" > +) > + > +(define_peephole2 > + [(set (match_operand:WORD 0 "int_reg_operand" "") > + (match_operand:WORD 1 "int_reg_operand" "")) > + (set (match_operand:CC 2 "cc_reg_operand" "") > + (compare:CC (match_dup 1) > + (const_int 0)))] > + "!cc_reg_not_cr0_operand (operands[2], CCmode)" > + [(parallel [(set (match_operand:CC 2 "cc_reg_operand" "=x") > + (compare:CC (match_operand:GPR 1 "int_reg_operand" "r") > + (const_int 0))) > + (set (match_operand:WORD 0 "int_reg_operand" "=r") > + (match_dup 1))])] > + "" > +) > + > (define_split > [(set (match_operand:CC 2 "cc_reg_not_cr0_operand") > - (compare:CC (match_operand:P 1 "gpc_reg_operand") > + (compare:CC (match_operand:WORD 1 "gpc_reg_operand") > (const_int 0))) > - (set (match_operand:P 0 "gpc_reg_operand") (match_dup 1))] > + (set (match_operand:WORD 0 "gpc_reg_operand") (match_dup 1))] > "reload_completed" > [(set (match_dup 0) (match_dup 1)) > (set (match_dup 2) > diff --git a/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_32.c b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_32.c > new file mode 100644 > index 00000000000..29234dea7c7 > --- /dev/null > +++ b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_32.c > @@ -0,0 +1,60 @@ > +/* { dg-do compile { target powerpc*-*-* } } */ The test case gcc/testsuite/gcc.target/powerpc/regnames-1.c adopting "-mregnames" has the selector { target powerpc*-*-linux* }, I just had a testing on aix, option -mregnames isn't supported there. So I think we have to use the same selector here. The others looks good. Thanks! BR, Kewen > +/* { dg-skip-if "" { has_arch_ppc64 } } */ > +/* { dg-options "-O2 -mregnames" } */ > + > +/* Following instruction sequence is found in assembly of > + Perl_block_start, which is a function of op.c in SPEC2017 > + perlbench. It can be never combined to a move and compare > + instruction in combine pass. A peephole pattern is needed to > + converted the sequence to a "mr." instruction. > + > + cmpdi 0,9,0 > + mr 12,9 > + > + This test case is an analogue of the source code and verifies > + if the peephole2 patterns work. > +*/ > + > +int __RTL (startwith ("peephole2")) compare_move_peephole () > +{ > +(function "compare_move_peephole" > + (insn-chain > + (block 2 > + (edge-from entry (flags "FALLTHRU")) > + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) > + (cinsn 8 (set (reg:CC %cr0) > + (compare:CC (reg:SI %r3) > + (const_int 0)))) > + (cinsn 2 (set (reg:SI %r4) > + (reg:SI %r3))) > + ;; Extra insn to avoid the above being deleted by DCE. > + (cinsn 18 (use (reg:SI %r4))) > + (cinsn 19 (use (reg:CC %cr0))) > + (edge-to exit (flags "FALLTHRU")) > + ) ;; block 2 > + ) ;; insn-chain > +) ;; function "main" > +} > + > +int __RTL (startwith ("peephole2")) move_compare_peephole () > +{ > +(function "move_compare_peephole" > + (insn-chain > + (block 2 > + (edge-from entry (flags "FALLTHRU")) > + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) > + (cinsn 2 (set (reg:SI %r4) > + (reg:SI %r3))) > + (cinsn 8 (set (reg:CC %cr0) > + (compare:CC (reg:SI %r3) > + (const_int 0)))) > + ;; Extra insn to avoid the above being deleted by DCE. > + (cinsn 18 (use (reg:SI %r4))) > + (cinsn 19 (use (reg:CC %cr0))) > + (edge-to exit (flags "FALLTHRU")) > + ) ;; block 2 > + ) ;; insn-chain > +) ;; function "main" > +} > + > +/* { dg-final { scan-assembler-times {\mmr\.} 2 } } */ > diff --git a/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_64.c b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_64.c > new file mode 100644 > index 00000000000..dd360033dbd > --- /dev/null > +++ b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_64.c > @@ -0,0 +1,60 @@ > +/* { dg-do compile { target powerpc*-*-* } } */ > +/* { dg-options "-O2 -mregnames" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > + > +/* Following instruction sequence is found in assembly of > + Perl_block_start, which is a function of op.c in SPEC2017 > + perlbench. It can be never combined to a move and compare > + instruction in combine pass. A peephole pattern is needed to > + converted the sequence to a "mr." instruction. > + > + cmpdi 0,9,0 > + mr 12,9 > + > + This test case is an analogue of the source code and verifies > + if the peephole2 patterns work. > +*/ > + > +int __RTL (startwith ("peephole2")) compare_move_peephole () > +{ > +(function "compare_move_peephole" > + (insn-chain > + (block 2 > + (edge-from entry (flags "FALLTHRU")) > + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) > + (cinsn 8 (set (reg:CC %cr0) > + (compare:CC (reg:DI %r3) > + (const_int 0)))) > + (cinsn 2 (set (reg:DI %r4) > + (reg:DI %r3))) > + ;; Extra insn to avoid the above being deleted by DCE. > + (cinsn 18 (use (reg:DI %r4))) > + (cinsn 19 (use (reg:CC %cr0))) > + (edge-to exit (flags "FALLTHRU")) > + ) ;; block 2 > + ) ;; insn-chain > +) ;; function "main" > +} > + > +int __RTL (startwith ("peephole2")) move_compare_peephole () > +{ > +(function "move_compare_peephole" > + (insn-chain > + (block 2 > + (edge-from entry (flags "FALLTHRU")) > + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) > + (cinsn 2 (set (reg:DI %r4) > + (reg:DI %r3))) > + (cinsn 8 (set (reg:CC %cr0) > + (compare:CC (reg:DI %r3) > + (const_int 0)))) > + ;; Extra insn to avoid the above being deleted by DCE. > + (cinsn 18 (use (reg:DI %r4))) > + (cinsn 19 (use (reg:CC %cr0))) > + (edge-to exit (flags "FALLTHRU")) > + ) ;; block 2 > + ) ;; insn-chain > +) ;; function "main" > +} > + > +/* { dg-final { scan-assembler-times {\mmr\.} 2 } } */