LGTM. juzhe.zhong@rivai.ai From: demin.han Date: 2024-06-20 11:28 To: gcc-patches CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc Subject: [PATCH v2] RISC-V: Remove integer vector eqne pattern We can unify eqne and other comparison operations. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/predicates.md (comparison_except_eqge_operator): Only exclude ge (comparison_except_ge_operator): Ditto * config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern (expand_strcmp): Ditto * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove eqne patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto (*pred_eqne_extended_scalar_merge_tie_mask): Ditto (*pred_eqne_extended_scalar): Ditto (*pred_eqne_extended_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer-cmp-eqne.c: New test. Signed-off-by: demin.han --- v2 changes: 1. add test gcc/config/riscv/predicates.md | 4 +- gcc/config/riscv/riscv-string.cc | 4 +- .../riscv/riscv-vector-builtins-bases.cc | 3 - gcc/config/riscv/vector.md | 279 +----------------- .../riscv/rvv/base/integer-cmp-eqne.c | 66 +++++ 5 files changed, 81 insertions(+), 275 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 0fb5729fdcf..9971fabc587 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -568,8 +568,8 @@ (define_predicate "ltge_operator" (define_predicate "comparison_except_ltge_operator" (match_code "eq,ne,le,leu,gt,gtu")) -(define_predicate "comparison_except_eqge_operator" - (match_code "le,leu,gt,gtu,lt,ltu")) +(define_predicate "comparison_except_ge_operator" + (match_code "eq,ne,le,leu,gt,gtu,lt,ltu")) (define_predicate "ge_operator" (match_code "ge,geu")) diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 83e7afbd693..4702001bd9b 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -1342,7 +1342,7 @@ expand_rawmemchr (machine_mode mode, rtx dst, rtx haystack, rtx needle, /* Compare needle with haystack and store in a mask. */ rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec); rtx vmsops[] = {mask, eq, vec, needle}; - emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode), + emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode), riscv_vector::COMPARE_OP, vmsops, cnt); /* Find the first bit in the mask. */ @@ -1468,7 +1468,7 @@ expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes, = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX (mode)), vec1); rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)}; - emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode), + emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode), riscv_vector::COMPARE_OP, vmsops1, cnt); /* Look for vec1 != vec2 (includes vec2[i] == 0). */ diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 596b88cc8a3..6483faba39c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -718,9 +718,6 @@ public: if (CODE == GE || CODE == GEU) return e.use_compare_insn (CODE, code_for_pred_ge_scalar ( e.vector_mode ())); - else if (CODE == EQ || CODE == NE) - return e.use_compare_insn (CODE, code_for_pred_eqne_scalar ( - e.vector_mode ())); else return e.use_compare_insn (CODE, code_for_pred_cmp_scalar ( e.vector_mode ())); diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f8fae6557d9..fe18ee5b5f7 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4704,7 +4704,7 @@ (define_expand "@pred_cmp_scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand"))]) @@ -4722,7 +4722,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 3 "register_operand" " vr") (vec_duplicate:V_VLSI_QHS (match_operand: 4 "register_operand" " r"))]) @@ -4747,7 +4747,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -4769,7 +4769,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -4780,92 +4780,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand")) - (match_operand:V_VLSI_QHS 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_QHS 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since ;; we need to deal with SEW = 64 in RV32 system. (define_expand "@pred_cmp_scalar" @@ -4878,7 +4792,7 @@ (define_expand "@pred_cmp_scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand") (vec_duplicate:V_VLSI_D (match_operand: 5 "reg_or_int_operand"))]) @@ -4908,39 +4822,6 @@ (define_expand "@pred_cmp_scalar" DONE; }) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "reg_or_int_operand")) - (match_operand:V_VLSI_D 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" -{ - enum rtx_code code = GET_CODE (operands[3]); - if (riscv_vector::sew64_scalar_helper ( - operands, - /* scalar op */&operands[5], - /* vl */operands[6], - mode, - riscv_vector::has_vi_variant_p (code, operands[5]), - [] (rtx *operands, rtx boardcast_scalar) { - emit_insn (gen_pred_cmp (operands[0], operands[1], - operands[2], operands[3], operands[4], boardcast_scalar, - operands[6], operands[7], operands[8])); - }, - (riscv_vector::avl_type) INTVAL (operands[8]))) - DONE; -}) - (define_insn "*pred_cmp_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -4951,7 +4832,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (match_operand: 4 "register_operand" " r"))]) @@ -4965,30 +4846,6 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7))]) -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") @@ -5000,7 +4857,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -5022,7 +4879,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -5033,50 +4890,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -5087,7 +4900,7 @@ (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5113,7 +4926,7 @@ (define_insn "*pred_cmp_extended_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5135,7 +4948,7 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5147,76 +4960,6 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_insn "*pred_eqne_extended_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 4 "register_operand" " r"))) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR && !TARGET_64BIT" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_extended_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -(define_insn "*pred_eqne_extended_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; GE, vmsge.vx/vmsgeu.vx ;; ;; unmasked va >= x diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c new file mode 100644 index 00000000000..52b844cc29d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +#define CMP_VF_1(ID, S, OP) \ + vbool##S##_t test_1_##ID##_##S##_##OP (vint##S##m1_t op1, int##S##_t op2, \ + size_t vl) \ + { \ + return __riscv_vms##OP##_vx_i##S##m1_b##S (op1, op2, vl); \ + } + +CMP_VF_1 (0, 8, eq) +CMP_VF_1 (1, 16, eq) +CMP_VF_1 (2, 32, eq) +CMP_VF_1 (3, 64, eq) + +CMP_VF_1 (0, 8, ne) +CMP_VF_1 (1, 16, ne) +CMP_VF_1 (2, 32, ne) +CMP_VF_1 (3, 64, ne) + +#define CMP_VF_2(ID, S, OP, IMM) \ + vbool##S##_t test_2_##ID##_##S##_##OP (vint##S##m1_t op1, size_t vl) \ + { \ + return __riscv_vms##OP##_vx_i##S##m1_b##S (op1, IMM, vl); \ + } + +CMP_VF_2 (0, 8, eq, -16) +CMP_VF_2 (1, 8, eq, 15) +CMP_VF_2 (2, 8, eq, -17) +CMP_VF_2 (3, 8, eq, 16) +CMP_VF_2 (4, 16, eq, -16) +CMP_VF_2 (5, 16, eq, 15) +CMP_VF_2 (6, 16, eq, -17) +CMP_VF_2 (7, 16, eq, 16) +CMP_VF_2 (8, 32, eq, -16) +CMP_VF_2 (9, 32, eq, 15) +CMP_VF_2 (10, 32, eq, -17) +CMP_VF_2 (11, 32, eq, 16) +CMP_VF_2 (12, 64, eq, -16) +CMP_VF_2 (13, 64, eq, 15) +CMP_VF_2 (14, 64, eq, -17) +CMP_VF_2 (15, 64, eq, 16) + +CMP_VF_2 (0, 8, ne, -16) +CMP_VF_2 (1, 8, ne, 15) +CMP_VF_2 (2, 8, ne, -17) +CMP_VF_2 (3, 8, ne, 16) +CMP_VF_2 (4, 16, ne, -16) +CMP_VF_2 (5, 16, ne, 15) +CMP_VF_2 (6, 16, ne, -17) +CMP_VF_2 (7, 16, ne, 16) +CMP_VF_2 (8, 32, ne, -16) +CMP_VF_2 (9, 32, ne, 15) +CMP_VF_2 (10, 32, ne, -17) +CMP_VF_2 (11, 32, ne, 16) +CMP_VF_2 (12, 64, ne, -16) +CMP_VF_2 (13, 64, ne, 15) +CMP_VF_2 (14, 64, ne, -17) +CMP_VF_2 (15, 64, ne, 16) + +/* { dg-final { scan-assembler-times {vmseq\.vx} 12 } } */ +/* { dg-final { scan-assembler-times {vmsne\.vx} 12 } } */ +/* { dg-final { scan-assembler-times {vmseq\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {vmsne\.vi} 8 } } */ -- 2.45.1