Re: [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension

[Jeff Law <jeffreyalaw@gmail.com>]

On 12/19/23 10:28 PM, Jeff Law wrote:
> 
> 
> On 12/19/23 02:53, Sergei Lewis wrote:
>> gcc/ChangeLog
>>
>>      * config/riscv/riscv.md (movmem<mode>): Use 
>> riscv_vector::expand_block_move,
>>      if and only if we know the entire operation can be performed 
>> using one vector
>>      load followed by one vector store
>>
>> gcc/testsuite/ChangeLog
>>
>>      PR target/112109
>>      * gcc.target/riscv/rvv/base/movmem-1.c: New test
> So this needs to be regression tested.  Given that it only affects RVV, 
> I would suggest testing rv64gcv or rv32gcv.
> 
> 
> 
>> +(define_expand "movmem<mode>"
>> +  [(parallel [(set (match_operand:BLK 0 "general_operand")
>> +   (match_operand:BLK 1 "general_operand"))
>> +    (use (match_operand:P 2 "const_int_operand"))
>> +    (use (match_operand:SI 3 "const_int_operand"))])]
>> +  "TARGET_VECTOR"
>> +{
>> +  if ((INTVAL (operands[2]) >= TARGET_MIN_VLEN/8)
>> +    && (INTVAL (operands[2]) <= TARGET_MIN_VLEN)
>> +    && riscv_vector::expand_block_move (operands[0], operands[1],
>> +         operands[2]))
>> +    DONE;
>> +  else
>> +    FAIL;
>> +})
> Just a formatting nit.  A space on each side of the '/' operator above.
So I've fixed the formatting nit and tested on rv64gc and rv32gcv.  I 
hadn't planned to push it, but muscle memory kicked in and 1/3 has been 
pushed.

I'll be looking at 2/3 and 3/3 tomorrow (or possibly a bit tonight to 
take advantage of overnight CI runs).

jeff