From: Sandra Loosemore <sandra@codesourcery.com>
To: Tamar Christina <tamar.christina@arm.com>, <gcc-patches@gcc.gnu.org>
Cc: <nd@arm.com>, <rguenther@suse.de>
Subject: Re: [PATCH][committed]middle-end: Fix signbit tests when ran on ISA with support for masks.
Date: Wed, 10 Nov 2021 11:37:53 -0700 [thread overview]
Message-ID: <617e70fb-7250-d599-bf38-41899ed99e5c@codesourcery.com> (raw)
In-Reply-To: <patch-15054-tamar@arm.com>
On 11/10/21 4:54 AM, Tamar Christina via Gcc-patches wrote:
> Hi All,
>
> These test don't work on vector ISAs where the truth
> type don't match the vector mode of the operation.
>
> However I still want the tests to run on these
> architectures but just turn off the ISA modes that
> enable masks.
>
> This thus turns off SVE is it's on and turns off
> AVX512 if it's on.
>
> Regtested on aarch64-none-linux-gnu with SVE on,
> and x86_64-pc-linux-gnu with AVX512 on and no
> issues.
>
> Committed under the obvious rule.
>
> Thanks,
> Tamar
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/signbit-2.c: Turn of masks.
> * gcc.dg/signbit-5.c: Likewise.
I'm seeing this failure on nios2-elf:
FAIL: gcc.dg/signbit-2.c scan-tree-dump-times optimized "\\s+>\\s+{ 0,
0, 0, 0 }" 1
I don't understand what it is expecting to happen here. Should it be
skipped on this target, or restricted to ARM and x86? Adding some
comments to the testcase to explain the significance of that pattern
might be useful too.
-Sandra
next prev parent reply other threads:[~2021-11-10 18:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 11:54 Tamar Christina
2021-11-10 18:37 ` Sandra Loosemore [this message]
2021-11-10 18:53 ` Tamar Christina
2021-11-10 20:03 ` Sandra Loosemore
2021-11-11 13:24 ` Tamar Christina
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