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From: Jeff Law <jeffreyalaw@gmail.com>
To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH] RISC-V: Fix incorrect condition of EEW = 64 mode
Date: Wed, 12 Apr 2023 17:00:34 -0600	[thread overview]
Message-ID: <61f44459-8159-e4df-3ab8-268d055ab161@gmail.com> (raw)
In-Reply-To: <20230407011143.46004-1-juzhe.zhong@rivai.ai>



On 4/6/23 19:11, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> This patch should be merged before this patch:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614935.html
> 
> According to RVV ISA, the EEW = 64 is enable only when -march=*zve64*
> Current condition is incorrect, since -march=*zve32*_zvl64b will enable EEW = 64 which
> is incorrect.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-switch.def (ENTRY): Change to TARGET_VECTOR_ELEN_64.
Just to be clear, this was for gcc-14, right?  I don't see these modes 
in the current trunk.

jeff

  reply	other threads:[~2023-04-12 23:00 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-07  1:11 juzhe.zhong
2023-04-12 23:00 ` Jeff Law [this message]
2023-04-12 23:12   ` 钟居哲
2023-04-25  5:55 ` Jeff Law

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