From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) by sourceware.org (Postfix) with ESMTPS id 604C63858D33 for ; Fri, 5 May 2023 17:12:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 604C63858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-55a214572e8so30976537b3.0 for ; Fri, 05 May 2023 10:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683306761; x=1685898761; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=mP/VYFznnvp+9omRnX0LwAfiTzTEWR95XzX4jznnlpI=; b=oMuCmz98QeWSVMXwvqCJE+ALXZoj9Lc/rTgNE+yHgo3hgwk71Xv2zKB5jl0ZiAgzMu rUaY/lkmjIUETCbCfq5q4MtYrhfZvsySQ405tzO650a+F92YSJHiF7Xowktf6LFgUZga 3u2UsmMNMLvM4Dlvk5Vvby3C/6iZDSstC1lZHMinZi6we0ooEgmtAfKRq8kOFUfznxI2 FOiAhcgVEtpB2FJQLQUyZcCrKk0Afz3Q0Z+x449UNwMZKqFL0OZ8qeHgmvcLNKROAZy+ Nnv9MRxiY2ygGx6N8iyh6m/fpbp3oaNRejH5DK8IZCVIzTTnqoVA4llGcfv90bT/zj1j nr2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683306761; x=1685898761; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mP/VYFznnvp+9omRnX0LwAfiTzTEWR95XzX4jznnlpI=; b=Ay5kUaKDZ+BBvDuA1sluKK1xaI6SlY0uCr+2OQaX75cFj3Nlx5AHmxR1DPKfFlZ2LE hpWkhO3D5gAlVO0yhG57YanqlDbiqA6iSxZ+LQ+B1rT3IMxGmhvpRtYPicforZ2xSXu3 J1swzrFxDtqThCima5rkF+HwBE3mzg3/DWOIsWd4rfACauFjWTxov7dI9xZrdikOZqlL jiQdnStSndPQezOT97Lf4XmgNzQcWDYYVXJYFSrsIotWGKPhSOqhvNPiIj31TZZC4lwg 5zBZvnaHAIzQcjr0AxZ0MWJEHMJkPQrb67Q35QILWbeY697Y3MhpbJJnq2skDhme+UR2 lV4Q== X-Gm-Message-State: AC+VfDwEML6Xanzpjtj7ZwWjPxDIV2TLu94g2nrk7QdQJHACKNrL2FIx ZG3itMGvyRRT9vHE5dfretNvgw== X-Google-Smtp-Source: ACHHUZ7XGmEamnCtc2btsPAUxdrU6h7b5akku/LiKZx6cWmDyyoA2bjt7xdrcSULxszLxtK1Hq7uNw== X-Received: by 2002:a81:8388:0:b0:55a:29ec:64f7 with SMTP id t130-20020a818388000000b0055a29ec64f7mr2742663ywf.40.1683306761631; Fri, 05 May 2023 10:12:41 -0700 (PDT) Received: from [192.168.86.117] ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id h6-20020a0df706000000b00545a08184bdsm582663ywf.77.2023.05.05.10.12.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 May 2023 10:12:41 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------dViex0mjBaafkxr0vizpM6ti" Message-ID: <6243bc21-e983-15ec-cd43-f47915e29189@rivosinc.com> Date: Fri, 5 May 2023 13:12:40 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v6 0/9] RISC-V: autovec: Add autovec support Content-Language: en-US To: Kito Cheng , Jeff Law , Palmer Dabbelt , =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: gcc-patches@gcc.gnu.org References: <20230505154607.1155567-1-collison@rivosinc.com> From: Michael Collison In-Reply-To: X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,HTML_MESSAGE,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------dViex0mjBaafkxr0vizpM6ti Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Because everyone was commenting that we needed vector load/store support (including Juzhe). Juzhe specifically pointed me to his patch for the load/store patterns in his review of my code. Would you like me to remove the patterns? On 5/5/23 12:34, Kito Cheng wrote: > Errr, why you just mixed in JuZhe’s patch set into this patch set? > > Michael Collison 於 2023年5月5日 週五，23:47寫道： > > This series of patches adds foundational support for RISC-V > auto-vectorization support. These patches are based on the current > upstream rvv vector intrinsic support and is not a new > implementation. Most of the implementation consists of adding the > new vector cost model, the autovectorization patterns themselves > and target hooks. This implementation only provides support for > integer addition and subtraction as a proof of concept. This patch > set should not be construed to be feature complete. Based on > conversations with the community these patches are intended to lay > the groundwork for feature completion and collaboration within the > RISC-V community. > > These patches are largely based off the work of Juzhe Zhong > (juzhe.zhong@rivai.ai) of RiVAI. More > specifically the rvv-next branch at: > https://github.com/riscv-collab/riscv-gcc.git > is the foundation > of this patch set. > > As discussed on this list, if these patches are approved they will > be merged into a "auto-vectorization" branch once gcc-13 branches > for release. There are two known issues related to crashes (assert > failures) associated with tree vectorization; one of which I have > sent a patch for and have received feedback. > > Changes in v6: > - Incorporated upstream comments, added target hook for > TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT > > Changes in v5: > > - Incorporated upstream comments large to delete unnecessary code > > Changes in v4: > > - Added support for binary integer operations and test cases > - Fixed bug to support 8-bit integer vectorization > - Fixed several assert errors related to non-multiple of two > vector modes > > Changes in v3: > > - Removed the cost model and cost hooks based on feedback from > Richard Biener > - Used RVV_VUNDEF macro to fix failing patterns > > Changes in v2 > > - Updated ChangeLog entry to include RiVAI contributions > - Fixed ChangeLog email formatting > - Fixed gnu formatting issues in the code > > Kevin Lee (1): >   RISC-V:autovec: This patch supports 8 bit auto-vectorization in > riscv. > > Michael Collison (8): >   RISC-V: Add new predicates and function prototypes >   RISC-V: autovec: Export policy functions to global scope >   RISC-V:autovec: Add auto-vectorization support functions >   RISC-V:autovec: Add target vectorization hooks >   RISC-V:autovec: Add autovectorization patterns for binary integer & >     len_load/store >   RISC-V:autovec: Add autovectorization tests for add & sub >   vect: Verify that GET_MODE_NUNITS is a multiple of 2. >   RISC-V:autovec: Add autovectorization tests for binary integer > >  gcc/config/riscv/riscv-opts.h                 |  10 ++ >  gcc/config/riscv/riscv-protos.h               |   9 ++ >  gcc/config/riscv/riscv-v.cc                   |  91 ++++++++++++ >  gcc/config/riscv/riscv-vector-builtins.cc     |   4 +- >  gcc/config/riscv/riscv-vector-builtins.h      |   3 + >  gcc/config/riscv/riscv.cc                     | 130 > ++++++++++++++++++ >  gcc/config/riscv/riscv.md                     |   1 + >  gcc/config/riscv/vector-auto.md               |  74 ++++++++++ >  gcc/config/riscv/vector.md                    |   4 +- >  .../riscv/rvv/autovec/loop-add-rv32.c         |  25 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-add.c   |  25 ++++ >  .../riscv/rvv/autovec/loop-and-rv32.c         |  25 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-and.c   |  25 ++++ >  .../riscv/rvv/autovec/loop-div-rv32.c         |  27 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-div.c   |  27 ++++ >  .../riscv/rvv/autovec/loop-max-rv32.c         |  26 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-max.c   |  26 ++++ >  .../riscv/rvv/autovec/loop-min-rv32.c         |  26 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-min.c   |  26 ++++ >  .../riscv/rvv/autovec/loop-mod-rv32.c         |  27 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-mod.c   |  27 ++++ >  .../riscv/rvv/autovec/loop-mul-rv32.c         |  25 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-mul.c   |  25 ++++ >  .../riscv/rvv/autovec/loop-or-rv32.c          |  25 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-or.c    |  25 ++++ >  .../riscv/rvv/autovec/loop-sub-rv32.c         |  25 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-sub.c   |  25 ++++ >  .../riscv/rvv/autovec/loop-xor-rv32.c         |  25 ++++ >  .../gcc.target/riscv/rvv/autovec/loop-xor.c   |  25 ++++ >  gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    |   4 + >  gcc/tree-vect-slp.cc                          |   7 +- >  31 files changed, 843 insertions(+), 6 deletions(-) >  create mode 100644 gcc/config/riscv/vector-auto.md >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c >  create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c > > -- > 2.34.1 > --------------dViex0mjBaafkxr0vizpM6ti--