Thanks. I still sent V5 with fixing "dummy" into "vlmax"
and add more comments.

Thanks.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-07-07 20:34
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH V4] RISC-V: Support gather_load/scatter RVV auto-vectorization
Hi Juzhe,
 
thanks, the somewhat unified modulo is IMHO a more readable.
Could probably still be improved but OK with me for now.
 
> +   if (is_dummy_len)
> +     {
> +       rtx dummy_len = gen_reg_rtx (Pmode);
 
Can we call this is_vlmax_len/is_vlmax and vlmax_len or so?
 
> +  if (inner_offsize < inner_vsize)
> +    {
> +      /* 7.2. Vector Load/Store Addressing Modes.
> + If the vector offset elements are narrower than XLEN, they are
> + zero-extended to XLEN before adding to the ptr effective address. If
> + the vector offset elements are wider than XLEN, the least-significant
> + XLEN bits are used in the address calculation. An implementation must
> + raise an illegal instruction exception if the EEW is not supported for
> + offset elements.  */
> +      if (!zero_extend_p || (zero_extend_p && scale_log2 != 0))
 
Hehe I really thought we have a widening shift, well ;)
 
I see, the zero extension refers to this part of the GCC docs
"multiply the extended offset by operand 4;" 
 
and not to the RVV spec.  You could clarify this then, saying
that the RVV spec only refers to the scale_log == 0 case.
 
The rest LGTM now, no separate revision needed for those nits.
 
Regards
Robin