From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 587BE3858D20 for ; Tue, 11 Jul 2023 10:58:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 587BE3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=linux.vnet.ibm.com Received: from pps.filterd (m0353727.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36BAlnFq003719; Tue, 11 Jul 2023 10:58:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : from : subject : to : cc : references : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=8AHVoH4Miz77UqxD/mMXjco5h7CNTewmQ05NUa1WGLw=; b=Toj9A9ZJeAq/eZ0CSASvIhFC20P0YNlnQFhi8sb055JvroZxrdusSJ0qAU8R/CESBpn4 vhROBUkLd2xlDWai1vTzqwAPs/+pouHvNGDmU97876Zcrsd5MfpTW6nLzNdUjk5EEiCL eZYQ4rNWEsvKs2CG+dGRoJf6YEurp5zHbDKDfj2a71M16dYJcZ66hSxBeiNwdgdZ6CKY XtdiXJwNUbrEuSgs9sxbRqAeR/iNmEcqlgIqw3anLmWmTKybgndxlCOYsV/JvpWasWa2 HsOQETszPRzssZd+WjJNhsM9FcIvINzAzGdZ1usQKbAGC1Dr0ty1uI240Vjq3Ua3KesM PA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rs5mxg739-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jul 2023 10:58:02 +0000 Received: from m0353727.ppops.net (m0353727.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36BAqfSt017863; Tue, 11 Jul 2023 10:58:02 GMT Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rs5mxg72p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jul 2023 10:58:02 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 36B8lGtm026569; Tue, 11 Jul 2023 10:58:01 GMT Received: from smtprelay03.dal12v.mail.ibm.com ([9.208.130.98]) by ppma03dal.us.ibm.com (PPS) with ESMTPS id 3rpye5mnnh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jul 2023 10:58:01 +0000 Received: from smtpav03.dal12v.mail.ibm.com (smtpav03.dal12v.mail.ibm.com [10.241.53.102]) by smtprelay03.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36BAw0aw64553300 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 11 Jul 2023 10:58:00 GMT Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 58E3C58056; Tue, 11 Jul 2023 10:58:00 +0000 (GMT) Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7D8545803F; Tue, 11 Jul 2023 10:57:58 +0000 (GMT) Received: from [9.109.208.149] (unknown [9.109.208.149]) by smtpav03.dal12v.mail.ibm.com (Postfix) with ESMTP; Tue, 11 Jul 2023 10:57:58 +0000 (GMT) Message-ID: <62bc957d-4648-450b-9572-8570297696ce@linux.vnet.ibm.com> Date: Tue, 11 Jul 2023 16:27:56 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 From: P Jeevitha Subject: Re: [PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320] To: Peter Bergner , "Kewen.Lin" Cc: Segher Boessenkool , gcc-patches@gcc.gnu.org, David Edelsohn References: <64addcb2-4370-6885-a08e-e93e2b7e3ede@linux.ibm.com> Content-Language: en-US In-Reply-To: <64addcb2-4370-6885-a08e-e93e2b7e3ede@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: PWGWMMUK4hoiZKa4TvFyvI2Y9RUYDis4 X-Proofpoint-ORIG-GUID: R9gSTdDM88AA8SeTFxhXjbRjNzBoz9cW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-11_04,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 suspectscore=0 spamscore=0 mlxlogscore=896 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307110094 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 07/07/2023 A 12:11 am, Peter Bergner wrote: > I believe the untested patch below should also work, without having to scan > the (uncommonly used) options. Jeevitha, can you bootstrap and regtest the > patch below? Yeah Peter, Bootstrapped and regtested the below patch on powerpc64le-linux there was no regression. > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index d197c3f3289..7c356a73ac6 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -10160,9 +10160,13 @@ rs6000_conditional_register_usage (void) > for (i = 32; i < 64; i++) > fixed_regs[i] = call_used_regs[i] = 1; > > + /* For non PC-relative code, GPR2 is unavailable for register allocation. */ > + if (FIXED_R2 && !rs6000_pcrel_p ()) > + fixed_regs[2] = 1; > + > /* The TOC register is not killed across calls in a way that is > visible to the compiler. */ > - if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) > + if (fixed_regs[2] && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)) > call_used_regs[2] = 0; > > if (DEFAULT_ABI == ABI_V4 && flag_pic == 2) > diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h > index 3503614efbd..2a24fbdf9fd 100644 > --- a/gcc/config/rs6000/rs6000.h > +++ b/gcc/config/rs6000/rs6000.h > @@ -812,7 +812,7 @@ enum data_align { align_abi, align_opt, align_both }; > > #define FIXED_REGISTERS \ > {/* GPRs */ \ > - 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ > + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ > 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ > /* FPRs */ \ > 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ > > > >> Besides, IMHO we need a corresponding test case to cover this -ffixed-r2 handling. > > Good idea. I think we can duplicate the pr110320_2.c test case, replacing the > -mno-pcrel option with -ffixed-r2. Jeevitha, can you give that a try? Yeah, adding the new test cases along with the mentioned changes for the older ones below, diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_1.c b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c new file mode 100644 index 00000000000..a4ad34d9303 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c @@ -0,0 +1,22 @@ +/* PR target/110320 */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r11 and r12. That leaves RA to choose from r2 and the more + expensive non-volatile registers for the temporary to be assigned to, and + RA will always chooses the cheaper volatile r2 register. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_2.c b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c new file mode 100644 index 00000000000..9d6aefedd2e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c @@ -0,0 +1,21 @@ +/* PR target/110320 */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we don't use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r11 and r12. That only leaves RA to choose from the more + expensive non-volatile registers for the temporary to be assigned to. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_3.c b/gcc/testsuite/gcc.target/powerpc/pr110320_3.c new file mode 100644 index 00000000000..ea6c6188c8d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320_3.c @@ -0,0 +1,21 @@ +/* PR target/110320 */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r2 -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we don't use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r2, r11 and r12. That only leaves RA to choose from the more + expensive non-volatile registers for the temporary to be assigned to. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */