From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by sourceware.org (Postfix) with ESMTP id 7C53D3857C5C for ; Sat, 21 Nov 2020 17:03:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7C53D3857C5C Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-191-xSnpHGy7MlODUjVPvmYfSA-1; Sat, 21 Nov 2020 12:03:11 -0500 X-MC-Unique: xSnpHGy7MlODUjVPvmYfSA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 041801005D67; Sat, 21 Nov 2020 17:03:09 +0000 (UTC) Received: from localhost.localdomain (ovpn-113-152.phx2.redhat.com [10.3.113.152]) by smtp.corp.redhat.com (Postfix) with ESMTP id 345606085D; Sat, 21 Nov 2020 17:03:08 +0000 (UTC) Subject: Re: [PATCH 22/31] VAX: Ensure PIC mode address is adjustable with aligned bitfield insns To: "Maciej W. Rozycki" , gcc-patches@gcc.gnu.org Cc: Anders Magnusson , Paul Koning , Matt Thomas References: From: Jeff Law Message-ID: <63d75f9a-3832-4d21-3901-3c80509787d5@redhat.com> Date: Sat, 21 Nov 2020 10:03:06 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1 MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Nov 2020 17:03:17 -0000 On 11/19/20 8:35 PM, Maciej W. Rozycki wrote: > With the `*insv_aligned', `*extzv_aligned' and `*extv_aligned' insns we > are going to adjust the bitfield location if it is in memory, so only > allow such location addresses that can be offset, excluding external > symbol references in the PIC mode in particular. > > This fixes an ICE like: > > during RTL pass: final > In file included from .../gcc/testsuite/gcc.dg/torture/vshuf-v16qi.c:11: > .../gcc/testsuite/gcc.dg/torture/vshuf-main.inc: In function 'test_13': > .../gcc/testsuite/gcc.dg/torture/vshuf-main.inc:27:1: internal compiler error: in change_address_1, at emit-rtl.c:2275 > .../gcc/testsuite/gcc.dg/torture/vshuf-16.inc:16:1: note: in expansion of macro 'T' > .../gcc/testsuite/gcc.dg/torture/vshuf-main.inc:28:1: note: in expansion of macro 'TESTS' > 0x10a34b33 change_address_1 > .../gcc/emit-rtl.c:2275 > 0x10a358af adjust_address_1(rtx_def*, machine_mode, poly_int<1u, long>, int, int, int, poly_int<1u, long>) > .../gcc/emit-rtl.c:2409 > 0x11d2505f output_97 > .../gcc/config/vax/vax.md:806 > 0x10adec4b get_insn_template(int, rtx_insn*) > .../gcc/final.c:2070 > 0x10ae1c5b final_scan_insn_1 > .../gcc/final.c:3039 > 0x10ae2257 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*) > .../gcc/final.c:3152 > 0x10ade9a3 final_1 > .../gcc/final.c:2020 > 0x10ae6157 rest_of_handle_final > .../gcc/final.c:4658 > 0x10ae6697 execute > .../gcc/final.c:4736 > Please submit a full bug report, > with preprocessed source if appropriate. > Please include the complete backtrace with any bug report. > See for instructions. > compiler exited with status 1 > FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (internal compiler error) > > triggered by an RTL instruction like: > > (insn 97 96 98 (set (reg:SI 5 %r5 [88]) > (zero_extract:SI (mem/c:SI (symbol_ref:SI ("b") ) [0 b+0 S4 A128]) > (const_int 8 [0x8]) > (const_int 24 [0x18]))) ".../gcc/testsuite/gcc.dg/torture/vshuf-main.inc":28:1 97 {*extzv_aligned} > (nil)) > > and removes these regressions: > > FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (test for excess errors) > FAIL: gcc.dg/torture/vshuf-v4hi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v4hi.c -O2 (test for excess errors) > FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 (test for excess errors) > FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 (internal compiler error) > FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 (test for excess errors) > > However expand typically presents pseudo-registers rather than memory > references to these insns, so a further rework is required to make a > better use of the code variant they are supposed to produce. This at > least fixes the problem at hand. > > gcc/ > * config/vax/vax.md (*insv_aligned, *extzv_aligned) > (*extv_aligned): Also make sure the memory address of a bitfield > location can be adjusted in the PIC mode. OK jeff