From a53553878602c7050b4f027a19149ca643b11721 Mon Sep 17 00:00:00 2001 From: Saurabh Jha Date: Wed, 8 Nov 2023 14:33:35 +0000 Subject: [PATCH 1/1] Add a REG_P check for inc and dec for Arm MVE It is okay to have operands in MEM for inc and dec in Arm MVE. This patch introduces a REG_P check for inc and dec so that we don't get an ICE for the case of inc/dec on MEM. --- gcc/config/arm/arm.cc | 7 +++++-- gcc/testsuite/gcc.target/arm/mve/pr112337.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr112337.c diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 620ef7bfb2f..25a1ad736ad 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -13695,8 +13695,11 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) } code = GET_CODE (op); - if (code == POST_INC || code == PRE_DEC - || code == PRE_INC || code == POST_DEC) + if ((code == POST_INC + || code == PRE_DEC + || code == PRE_INC + || code == POST_DEC) + && REG_P (XEXP (op, 0))) { reg_no = arm_effective_regno (XEXP (op, 0), strict); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) diff --git a/gcc/testsuite/gcc.target/arm/mve/pr112337.c b/gcc/testsuite/gcc.target/arm/mve/pr112337.c new file mode 100644 index 00000000000..8f491990088 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/pr112337.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +#include + +void g(int32x4_t); +void f(int, int, int, short, int *p) { + int *bias = p; + for (;;) { + int32x4_t d = vldrwq_s32 (p); + bias += 4; + g(d); + } +} -- 2.34.1