From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98727 invoked by alias); 8 Oct 2016 17:33:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 98710 invoked by uid 89); 8 Oct 2016 17:33:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL,BAYES_40,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=6037, formally, sk:ebotcaz, U*ebotcazou X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 08 Oct 2016 17:33:20 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 0B20F812EF for ; Sat, 8 Oct 2016 19:33:19 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q9-g4hjeh8CE for ; Sat, 8 Oct 2016 19:33:18 +0200 (CEST) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id DBA9E812E6 for ; Sat, 8 Oct 2016 19:33:18 +0200 (CEST) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Make %icc a formally fixed register Date: Sat, 08 Oct 2016 17:33:00 -0000 Message-ID: <6585143.gpykmfgHlT@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-42-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart1555873.gAGkrgDcbk" Content-Transfer-Encoding: 7Bit X-SW-Source: 2016-10/txt/msg00537.txt.bz2 This is a multi-part message in MIME format. --nextPart1555873.gAGkrgDcbk Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Content-length: 281 It de facto was fixed already, since it belongs to no register class, so there is no functional change. Tested on SPARC/Solaris, applied on the mainline. 2016-10-08 Eric Botcazou * config/sparc/sparc.h (FIXED_REGISTERS): Add %icc. -- Eric Botcazou --nextPart1555873.gAGkrgDcbk Content-Disposition: attachment; filename="p.diff" Content-Transfer-Encoding: 7Bit Content-Type: text/x-patch; charset="UTF-8"; name="p.diff" Content-length: 1582 Index: config/sparc/sparc.h =================================================================== --- config/sparc/sparc.h (revision 240888) +++ config/sparc/sparc.h (working copy) @@ -603,7 +603,8 @@ extern enum cmodel sparc_cmodel; (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 32+32+32+4 == 100. Register 100 is used as the integer condition code register. - Register 101 is used as the soft frame pointer register. */ + Register 101 is used as the soft frame pointer register. + Register 102 is used as the general status register by VIS instructions. */ #define FIRST_PSEUDO_REGISTER 103 @@ -678,7 +679,7 @@ extern enum cmodel sparc_cmodel; 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ \ - 0, 0, 0, 0, 0, 1, 1} + 0, 0, 0, 0, 1, 1, 1} /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any @@ -885,12 +886,7 @@ extern int sparc_mode_class[]; have a class that is the union of FPCC_REGS with either of the others, it is important that it appear first. Otherwise the compiler will die trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its - constraints. - - It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine - may try to use it to hold an SImode value. See register_operand. - ??? Should %fcc[0123] be handled similarly? -*/ + constraints. */ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, --nextPart1555873.gAGkrgDcbk--