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From: Tobias Burnus <tobias@codesourcery.com>
To: <gcc-patches@gcc.gnu.org>, Jeff Law <law@redhat.com>,
	Richard Biener <rguenther@suse.de>
Cc: Roger Sayle <roger@nextmovesoftware.com>
Subject: PING**2 - [PATCH] middle-end: Support ABIs that pass FP values as wider integers.
Date: Wed, 23 Feb 2022 09:42:54 +0100	[thread overview]
Message-ID: <65b25eab-a831-db0d-3332-43fde9879efd@codesourcery.com> (raw)
In-Reply-To: <f4eeb170-ce43-e9d0-5af0-7feab3ce11bb@codesourcery.com>

PING**2 for the ME review or at least comments to that patch,
which fixes a build issue/ICE with nvptx (at least when bumping the
default -misa).

Patch: https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590139.html
(for gcc/cfgexpand.cc + gcc/expr.cc)

(There is some discussion by Tom and Roger about the BE in the patch
thread, which only not relate to the ME patch. But there is no ME-patch
comment so far.)

Thanks,

Tobias

On 17.02.22 15:35, Tobias Burnus wrote:
> PING for this cfgexpand.cc + expr.cc change by Roger.
>
> This is a pre-requisite for Roger's nvptx patch to avoid an ICE during
> bootstrap:
>
> * https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590250.html
>   "[PATCH] nvptx: Back-end portion of a fix for PR target/104489."
>   (see patch for additional reasoning for this patch)
> * See also https://gcc.gnu.org/PR104489
>    nvptx, sm_53: internal compiler error: in gen_rtx_SUBREG, at
> emit-rtl.cc:1022
>
> Thanks,
>
> Tobias
>
> On 09.02.22 21:12, Roger Sayle wrote:
>> This patch adds middle-end support for target ABIs that pass/return
>> floating point values in integer registers with precision wider than
>> the original FP mode.  An example, is the nvptx backend where 16-bit
>> HFmode registers are passed/returned as (promoted to) SImode registers.
>> Unfortunately, this currently falls foul of the various (recent?) sanity
>> checks that (very sensibly) prevent creating paradoxical SUBREGs of
>> floating point registers.  The approach below is to explicitly
>> perform the
>> conversion/promotion in two steps, via an integer mode of same precision
>> as the floating point value.  So on nvptx, 16-bit HFmode is initially
>> converted to 16-bit HImode (using SUBREG), then zero-extended to SImode,
>> and likewise when going the other way, parameters truncated to HImode
>> then converted to HFmode (using SUBREG).  These changes are localized
>> to expand_value_return and expanding DECL_RTL to support strange ABIs,
>> rather than inside convert_modes or gen_lowpart, as mismatched
>> precision integer/FP conversions should be explicit in the RTL,
>> and these semantics not generally visible/implicit in user code.
>>
>> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
>> and make -k check with no new failures, and on nvptx-none, where it is
>> the middle-end portion of a pair of patches to allow the default ISA to
>> be advanced.  Ok for mainline?
>>
>>
>> 2022-02-09  Roger Sayle  <roger@nextmovesoftware.com>
>>
>> gcc/ChangeLog
>>         * cfgexpand.cc (expand_value_return): Allow backends to promote
>>         a scalar floating point return value to a wider integer mode.
>>         * expr.cc (expand_expr_real_1) [expand_decl_rtl]: Likewise,
>> allow
>>         backends to promote scalar FP PARM_DECLs to wider integer modes.
>>
>>
>> Thanks in advance,
>> Roger
>> --
>>
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  reply	other threads:[~2022-02-23  8:43 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-09 20:12 Roger Sayle
2022-02-17 14:35 ` PING - " Tobias Burnus
2022-02-23  8:42   ` Tobias Burnus [this message]
2022-02-28  9:41     ` PING**3 " Tobias Burnus
2022-02-28 12:54       ` Richard Biener
2022-03-02 19:18         ` Jeff Law
2022-03-14  8:06           ` PING**4 " Tom de Vries
2022-03-14  8:39             ` Roger Sayle
2022-03-14  9:09               ` Richard Biener
2022-03-14  9:46                 ` Roger Sayle
2022-03-14 10:14                   ` Richard Biener
2022-03-14 11:49                     ` Roger Sayle
2022-03-14 13:27                       ` Richard Biener
2022-03-14 14:30                         ` Roger Sayle
2022-03-14 14:40                           ` Richard Biener
2022-03-14 15:31                           ` Richard Sandiford
2022-03-14 14:59                 ` Jeff Law
2022-03-14 15:08               ` Jeff Law
2022-02-22 15:42 ` Tom de Vries
2022-02-22 16:08   ` Roger Sayle
2022-02-22 22:09     ` Tom de Vries
2022-02-22 23:19       ` Roger Sayle
2022-03-14 15:30 ` Jeff Law
2022-03-14 17:24   ` Roger Sayle

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