From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 11BC43857431 for ; Thu, 10 Jun 2021 09:32:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 11BC43857431 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15A94EqA029878; Thu, 10 Jun 2021 05:32:31 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 393bkaqkc8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Jun 2021 05:32:31 -0400 Received: from m0098420.ppops.net (m0098420.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 15A94Hx8030207; Thu, 10 Jun 2021 05:32:31 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 393bkaqkbq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Jun 2021 05:32:31 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 15A9Hcfc019014; Thu, 10 Jun 2021 09:32:29 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma03ams.nl.ibm.com with ESMTP id 3900w8jqdc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Jun 2021 09:32:29 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 15A9WRih31523164 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Jun 2021 09:32:27 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 37F2E4C044; Thu, 10 Jun 2021 09:32:27 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 596624C046; Thu, 10 Jun 2021 09:32:25 +0000 (GMT) Received: from KewenLins-MacBook-Pro.local (unknown [9.197.254.48]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 10 Jun 2021 09:32:25 +0000 (GMT) Subject: Re: [PATCH] rs6000: Support more short/char to float conversion To: Segher Boessenkool Cc: GCC Patches , Bill Schmidt , David Edelsohn References: <20210609232306.GM18427@gate.crashing.org> From: "Kewen.Lin" Message-ID: <65fe2285-8a2e-751d-c008-ed369d0c954a@linux.ibm.com> Date: Thu, 10 Jun 2021 17:32:23 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <20210609232306.GM18427@gate.crashing.org> Content-Type: multipart/mixed; boundary="------------B87F53CFC429342F411DBDAC" Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: wAPb9wfErfXLScL2KniyI11RZwXtxVfl X-Proofpoint-GUID: j1ak7jzS-xK-D5P69pnyIvE0sxmwwtpQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-10_05:2021-06-10, 2021-06-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0 adultscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106100059 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, MIME_CHARSET_FARAWAY, NICE_REPLY_A, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Jun 2021 09:32:33 -0000 This is a multi-part message in MIME format. --------------B87F53CFC429342F411DBDAC Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 8bit Hi Segher, Thanks for the review! on 2021/6/10 ÉÏÎç7:23, Segher Boessenkool wrote: > Hi! > > On Fri, May 07, 2021 at 10:30:38AM +0800, Kewen.Lin wrote: >> For some cases that when we load unsigned char/short values from >> the appropriate unsigned char/short memories and convert them to >> double/single precision floating point value, there would be >> implicit conversions to int first. It makes GCC not leverage the >> P9 instructions lxsibzx/lxsihzx. This patch is to add the related >> define_insn_and_split to support this kind of scenario. > >> +/* { dg-final { scan-assembler "lxsibzx" } } */ >> +/* { dg-final { scan-assembler "lxsihzx" } } */ >> +/* { dg-final { scan-assembler "vextsb2d" } } */ >> +/* { dg-final { scan-assembler "vextsh2d" } } */ > > On my unpatched compiler all these already work, but you say they don't? > Sorry for the confusion, the patch is to handle the unsigned char and short but the test case also has the test coverage on signed char and short, which follows the existing cases p9-fpcvt-{1,2}.c. As you stated, the signed part of cases are fine. > For the first two I get > lxsibzx 33,0,3 > vextsb2d 0,1 > xscvsxddp 0,32 > fadd 1,0,1 > blr > and > lbz 9,0(3) > mtvsrwa 0,9 > fcfid 0,0 > fadd 1,0,1 > blr > is that different for you? > I got the same output without the patch, applying the patch the second one becomes into: lxsibzx 0,0,3 fcfid 0,0 fadd 1,0,1 blr > In either case, use \m and \M please. > Fixed. >> +/* { dg-final { scan-assembler-not "mfvsrd" } } */ >> +/* { dg-final { scan-assembler-not "mfvsrwz" } } */ >> +/* { dg-final { scan-assembler-not "mtvsrd" } } */ >> +/* { dg-final { scan-assembler-not "mtvsrwa" } } */ >> +/* { dg-final { scan-assembler-not "mtvsrwz" } } */ > > Here as well, or you could just do > > /* { dg-final { scan-assembler-not "\mm[tf]vsr" } } */ > > in this case, since no VSR<->GPR moves should happen at all. > Thanks, updated accordingly. The patch v2 is attached, does it look better? BR, Kewen ------ gcc/ChangeLog: * config/rs6000/rs6000.md (floatsi2_lfiwax__mem_zext): New define_insn_and_split. gcc/testsuite/ChangeLog: * gcc.target/powerpc/p9-fpcvt-3.c: New test. --------------B87F53CFC429342F411DBDAC Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="conv_v2.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="conv_v2.diff" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3f59b544f6a..0574e10f923 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5524,6 +5524,27 @@ (define_insn_and_split "floatsi2_lfiwax_mem" [(set_attr "length" "8") (set_attr "type" "fpload")]) +(define_insn_and_split "floatsi2_lfiwax__mem_zext" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (float:SFDF + (zero_extend:SI + (match_operand:QHI 1 "indexed_or_indirect_operand" "Z,Z")))) + (clobber (match_scratch:DI 2 "=d,wa"))] + "TARGET_HARD_FLOAT && && TARGET_P9_VECTOR + && TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& 1" + [(pc)] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (DImode); + emit_insn (gen_zero_extendhidi2 (operands[2], operands[1])); + emit_insn (gen_floatdi2 (operands[0], operands[2])); + DONE; +} + [(set_attr "length" "8") + (set_attr "type" "fpload")]) + (define_insn "lfiwzx" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa,wa,wa") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")] diff --git a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c new file mode 100644 index 00000000000..19701c84add --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +/* Note that for unsigned cases, the differences from those ones in + p9-fpcvt-2.c is that they will be converted to int implicitly first + and then to floating point. */ + +double sc_df (signed char *p, double df) { return *p + df; } +double uc_df (unsigned char *p, double df) { return *p + df; } +double ss_df (signed short *p, double df) { return *p + df; } +double us_df (unsigned short *p, double df) { return *p + df; } + +float sc_sf (signed char *p, float sf) { return *p + sf; } +float uc_sf (unsigned char *p, float sf) { return *p + sf; } +float ss_sf (signed short *p, float sf) { return *p + sf; } +float us_sf (unsigned short *p, float sf) { return *p + sf; } + +/* { dg-final { scan-assembler {\mlxsibzx\M} } } */ +/* { dg-final { scan-assembler {\mlxsihzx\M} } } */ +/* { dg-final { scan-assembler {\mvextsb2d\M} } } */ +/* { dg-final { scan-assembler {\mvextsh2d\M} } } */ +/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */ --------------B87F53CFC429342F411DBDAC--