From: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@caviumnetworks.com>
To: Marcus Shawcroft <marcus.shawcroft@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: RE: [PATCH, AArch64] Compare instruction in shift_extend mode
Date: Wed, 17 Apr 2013 13:19:00 -0000 [thread overview]
Message-ID: <66f9c26154ca4916a3b92b5ebb9e8910@SN2PR07MB029.namprd07.prod.outlook.com> (raw)
In-Reply-To: <516D58C7.5000306@arm.com>
[-- Attachment #1: Type: text/plain, Size: 415 bytes --]
Hi,
>> I suggest for this one test case either making it compile only and
>> dropping main() such that the pattern match only looks in the
>> assembled output of the cmp_* functions
The testcase will check only for assembly pattern of the instruction
as per your suggestion.
Please find attached the modified patch let me know if there should
be any further modifications in it.
Thanks,
Naveen
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: cmp_shift_ext.patch --]
[-- Type: text/x-patch; name="cmp_shift_ext.patch", Size: 1870 bytes --]
--- gcc/config/aarch64/aarch64.md 2013-04-17 11:18:29.453576713 +0530
+++ gcc/config/aarch64/aarch64.md 2013-04-17 15:22:36.161492471 +0530
@@ -2311,6 +2311,18 @@
(set_attr "mode" "<GPI:MODE>")]
)
+(define_insn "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>"
+ [(set (reg:CC_SWP CC_REGNUM)
+ (compare:CC_SWP (ashift:GPI
+ (ANY_EXTEND:GPI
+ (match_operand:ALLX 0 "register_operand" "r"))
+ (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
+ (match_operand:GPI 2 "register_operand" "r")))]
+ ""
+ "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
+ [(set_attr "v8type" "alus_ext")
+ (set_attr "mode" "<GPI:MODE>")]
+)
;; -------------------------------------------------------------------
;; Store-flag and conditional select insns
--- gcc/testsuite/gcc.target/aarch64/cmp.c 1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/cmp.c 2013-04-17 15:23:36.121492125 +0530
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+ if ((a >> 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+ if ((a >> 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+ if (((s64)a << 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
next prev parent reply other threads:[~2013-04-17 10:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-12 13:10 Hurugalawadi, Naveen
2013-04-12 15:47 ` Richard Earnshaw
2013-04-15 9:47 ` Hurugalawadi, Naveen
2013-04-16 20:24 ` Marcus Shawcroft
2013-04-17 13:19 ` Hurugalawadi, Naveen [this message]
2013-04-25 13:43 ` Marcus Shawcroft
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