* [PATCH] store-merging: Avoid ICEs on roughly ~0ULL/8 sized stores [PR105094]
@ 2022-03-30 7:53 Jakub Jelinek
2022-03-30 8:09 ` Richard Biener
0 siblings, 1 reply; 2+ messages in thread
From: Jakub Jelinek @ 2022-03-30 7:53 UTC (permalink / raw)
To: Richard Biener; +Cc: gcc-patches
Hi!
On the following testcase on 64-bit targets, store-merging sees
a MEM_REF store from {} ctor with "negative" bitsize where bitoff + bitsize
wraps around to very small end offset. This later confuses the code
so that it allocates just a few bytes of memory but fills in huge amounts of
it. Later on there is a param_store_merging_max_size size check but due to
the wrap-around we pass that.
The following patch punts on such large bitsizes.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2022-03-30 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/105094
* gimple-ssa-store-merging.cc (mem_valid_for_store_merging): Punt if
bitsize <= 0 rather than just == 0.
* gcc.dg/pr105094.c: New test.
--- gcc/gimple-ssa-store-merging.cc.jj 2022-02-04 14:36:55.000000000 +0100
+++ gcc/gimple-ssa-store-merging.cc 2022-03-29 12:06:44.918286242 +0200
@@ -4940,7 +4940,7 @@ mem_valid_for_store_merging (tree mem, p
tree base_addr = get_inner_reference (mem, &bitsize, &bitpos, &offset, &mode,
&unsignedp, &reversep, &volatilep);
*pbitsize = bitsize;
- if (known_eq (bitsize, 0))
+ if (known_le (bitsize, 0))
return NULL_TREE;
if (TREE_CODE (mem) == COMPONENT_REF
--- gcc/testsuite/gcc.dg/pr105094.c.jj 2022-03-29 12:32:16.871391545 +0200
+++ gcc/testsuite/gcc.dg/pr105094.c 2022-03-29 12:30:51.667609971 +0200
@@ -0,0 +1,13 @@
+/* PR tree-optimization/105094 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct S { short a; char b[~(__SIZE_TYPE__)0 / __CHAR_BIT__ - 1]; };
+void bar (struct S *);
+
+void
+foo (void)
+{
+ struct S s = { 5 };
+ bar (&s);
+}
Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] store-merging: Avoid ICEs on roughly ~0ULL/8 sized stores [PR105094]
2022-03-30 7:53 [PATCH] store-merging: Avoid ICEs on roughly ~0ULL/8 sized stores [PR105094] Jakub Jelinek
@ 2022-03-30 8:09 ` Richard Biener
0 siblings, 0 replies; 2+ messages in thread
From: Richard Biener @ 2022-03-30 8:09 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: gcc-patches
On Wed, 30 Mar 2022, Jakub Jelinek wrote:
> Hi!
>
> On the following testcase on 64-bit targets, store-merging sees
> a MEM_REF store from {} ctor with "negative" bitsize where bitoff + bitsize
> wraps around to very small end offset. This later confuses the code
> so that it allocates just a few bytes of memory but fills in huge amounts of
> it. Later on there is a param_store_merging_max_size size check but due to
> the wrap-around we pass that.
>
> The following patch punts on such large bitsizes.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
OK.
> 2022-03-30 Jakub Jelinek <jakub@redhat.com>
>
> PR tree-optimization/105094
> * gimple-ssa-store-merging.cc (mem_valid_for_store_merging): Punt if
> bitsize <= 0 rather than just == 0.
>
> * gcc.dg/pr105094.c: New test.
>
> --- gcc/gimple-ssa-store-merging.cc.jj 2022-02-04 14:36:55.000000000 +0100
> +++ gcc/gimple-ssa-store-merging.cc 2022-03-29 12:06:44.918286242 +0200
> @@ -4940,7 +4940,7 @@ mem_valid_for_store_merging (tree mem, p
> tree base_addr = get_inner_reference (mem, &bitsize, &bitpos, &offset, &mode,
> &unsignedp, &reversep, &volatilep);
> *pbitsize = bitsize;
> - if (known_eq (bitsize, 0))
> + if (known_le (bitsize, 0))
> return NULL_TREE;
>
> if (TREE_CODE (mem) == COMPONENT_REF
> --- gcc/testsuite/gcc.dg/pr105094.c.jj 2022-03-29 12:32:16.871391545 +0200
> +++ gcc/testsuite/gcc.dg/pr105094.c 2022-03-29 12:30:51.667609971 +0200
> @@ -0,0 +1,13 @@
> +/* PR tree-optimization/105094 */
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +struct S { short a; char b[~(__SIZE_TYPE__)0 / __CHAR_BIT__ - 1]; };
> +void bar (struct S *);
> +
> +void
> +foo (void)
> +{
> + struct S s = { 5 };
> + bar (&s);
> +}
>
> Jakub
>
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg,
Germany; GF: Ivo Totev; HRB 36809 (AG Nuernberg)
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