public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
From: Jeff Law <jeffreyalaw@gmail.com>
To: Alexandre Oliva <oliva@adacore.com>, gcc-patches@gcc.gnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Lehua Ding <lehua.ding@rivai.ai>,
	Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: Re: [PATCH] RISC-V: Revert the convert from vmv.s.x to vmv.v.i
Date: Fri, 23 Feb 2024 00:37:51 -0700	[thread overview]
Message-ID: <68381560-c776-4f37-b369-cd911155c2f5@gmail.com> (raw)
In-Reply-To: <or8r3fpy9d.fsf@lxoliva.fsfla.org>



On 2/19/24 21:15, Alexandre Oliva wrote:
> This backport is the first of two required for the pr111935 testcase,
> already backported to gcc-13, to pass on riscv64-elf and riscv32-elf.
> The V_VLS mode iterator, used in the original patch, is not available in
> gcc-13, and I thought that would be too much to backport (and maybe so
> are these two patches, WDYT?), so I changed it to V, to match the
> preexisting gcc-13 pattern.  Regstrapped on x86_64-linux-gnu, along with
> other backports, and tested manually on riscv64-elf.  Ok to install?
> 
> From: Lehua Ding <lehua.ding@rivai.ai>
> 
> Hi,
> 
> This patch revert the convert from vmv.s.x to vmv.v.i and add new pattern
> optimize the special case when the scalar operand is zero.
> 
> Currently, the broadcast pattern where the scalar operand is a imm
> will be converted to vmv.v.i from vmv.s.x and the mask operand will be
> converted from 00..01 to 11..11. There are some advantages and
> disadvantages before and after the conversion after discussing
> with Juzhe offline and we chose not to do this transform.
> 
> Before:
> 
>    Advantages: The vsetvli info required by vmv.s.x has better compatibility since
>    vmv.s.x only required SEW and VLEN be zero or one. That mean there
>    is more opportunities to combine with other vsetlv infos in vsetvl pass.
> 
>    Disadvantages: For non-zero scalar imm, one more `li rd, imm` instruction
>    will be needed.
> 
> After:
> 
>    Advantages: No need `li rd, imm` instruction since vmv.v.i support imm operand.
> 
>    Disadvantages: Like before's advantages. Worse compatibility leads to more
>    vsetvl instrunctions need.
> 
> Consider the bellow C code and asm after autovec.
> there is an extra insn (vsetivli zero, 1, e32, m1, ta, ma)
> after converted vmv.s.x to vmv.v.i.
> 
> ```
> int foo1(int* restrict a, int* restrict b, int *restrict c, int n) {
>      int sum = 0;
>      for (int i = 0; i < n; i++)
>        sum += a[i] * b[i];
> 
>      return sum;
> }
> ```
> 
> asm (Before):
> 
> ```
> foo1:
>          ble     a3,zero,.L7
>          vsetvli a2,zero,e32,m1,ta,ma
>          vmv.v.i v1,0
> .L6:
>          vsetvli a5,a3,e32,m1,tu,ma
>          slli    a4,a5,2
>          sub     a3,a3,a5
>          vle32.v v2,0(a0)
>          vle32.v v3,0(a1)
>          add     a0,a0,a4
>          add     a1,a1,a4
>          vmacc.vv        v1,v3,v2
>          bne     a3,zero,.L6
>          vsetvli a2,zero,e32,m1,ta,ma
>          vmv.s.x v2,zero
>          vredsum.vs      v1,v1,v2
>          vmv.x.s a0,v1
>          ret
> .L7:
>          li      a0,0
>          ret
> ```
> 
> asm (After):
> 
> ```
> foo1:
>          ble     a3,zero,.L4
>          vsetvli a2,zero,e32,m1,ta,ma
>          vmv.v.i v1,0
> .L3:
>          vsetvli a5,a3,e32,m1,tu,ma
>          slli    a4,a5,2
>          sub     a3,a3,a5
>          vle32.v v2,0(a0)
>          vle32.v v3,0(a1)
>          add     a0,a0,a4
>          add     a1,a1,a4
>          vmacc.vv        v1,v3,v2
>          bne     a3,zero,.L3
>          vsetivli        zero,1,e32,m1,ta,ma
>          vmv.v.i v2,0
>          vsetvli a2,zero,e32,m1,ta,ma
>          vredsum.vs      v1,v1,v2
>          vmv.x.s a0,v1
>          ret
> .L4:
>          li      a0,0
>          ret
> ```
> 
> Best,
> Lehua
> 
> Co-Authored-By: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/predicates.md (vector_const_0_operand): New.
> 	* config/riscv/vector.md (*pred_broadcast<mode>_zero): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/rvv/base/scalar_move-5.c: Update.
> 	* gcc.target/riscv/rvv/base/scalar_move-6.c: Ditto.
I wouldn't backport this.  Vector isn't something that's really expected 
to work with gcc-13.  Yea, you can do a bit of intrinsics, but that's it.

Jeff


  reply	other threads:[~2024-02-23  7:37 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-20  4:15 Alexandre Oliva
2024-02-23  7:37 ` Jeff Law [this message]
  -- strict thread matches above, loose matches on Subject: below --
2023-08-11  9:01 Lehua Ding
2023-08-11 15:04 ` Jeff Law
2023-08-11 15:43   ` Lehua Ding
2023-08-11 15:48     ` Jeff Law
2023-08-11 23:02 ` Jeff Law
2023-08-12  4:09   ` Lehua Ding

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=68381560-c776-4f37-b369-cd911155c2f5@gmail.com \
    --to=jeffreyalaw@gmail.com \
    --cc=andrew@sifive.com \
    --cc=gcc-patches@gcc.gnu.org \
    --cc=jim.wilson.gcc@gmail.com \
    --cc=juzhe.zhong@rivai.ai \
    --cc=kito.cheng@sifive.com \
    --cc=lehua.ding@rivai.ai \
    --cc=oliva@adacore.com \
    --cc=palmer@dabbelt.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).