RE: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu <ahsu@marvell.com>]

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Hi Ramana,

Attached is the patch for marvell-pj4.md to fix the simple_alu_shift category.
Thanks for your kindly help.

Cheers,
Yi-Hsiu, Hsu

-----Original Message-----
From: Ramana Radhakrishnan [mailto:ramrad01@arm.com] 
Sent: Friday, January 18, 2013 10:28 PM
To: Yi-Hsiu Hsu
Cc: gcc-patches@gcc.gnu.org ;
Subject: Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
> marvell-pj4 is added to BE8_LINK_SPEC.

Sorry about the time it's taken to finish this patch up. I seem to have missed this one in the review process.

I've now applied the attached patch after taking into account the recent attribute changes and treated alu_reg and simple_alu_imm as you have treated alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.

Additionally I've removed tune_marvell as that seems redundant at this point of time - an additional attribute and testing that appears to be unnecessary instead of just one more inequality test.

The only part I'm not sure about is how to treat the simple_alu_shift category here , so a patch to handle them in the pj4 pipeline description would be welcome.


Thanks
Ramana

2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

         * config/arm/marvell-pj4.md: New file.
         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
         * config/arm/arm.md (generic_sched): Add marvell_pj4.
         (generic_vfp): Likewise.
         * config/arm/arm-cores.def: Add marvell-pj4.
         * config/arm/arm-tune.md: Regenerate.
         * config/arm/arm-tables.opt: Regenerate.
         * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
         * doc/invoke.texi: Document marvell-pj4.

>
> Modified patch is attached.
>
> Thanks!
>
> B.R.
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
> Sent: Thursday, June 14, 2012 2:19 AM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>> Hi,
>>
>> This patch maintains Marvell PJ4 cores pipeline description.
>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>
>>         * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>         * config/arm/arm-cores.def: Add core marvell-pj4.
>>         * config/arm/arm-tune.md: Regenerated.
>>         * config/arm/arm-tables.opt: Regenerated.
>>         * doc/invoke.texi: Added entry for marvell-pj4.
>
> This command line option should also be added to BE8_LINK_SPEC similar 
> to what's done for the other v7-a cores.
>
> Ok with that change.
>
> regards,
> Ramana
>
>
>
>>
>>
>> Thanks!
>>
>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>

[-- Attachment #2: pj4.patch --]
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diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index cbf3110..fcbd31f 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -41,54 +41,54 @@
 
 (define_insn_reservation "pj4_alu_e1" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (not (eq_attr "conds" "set"))
        (eq_attr "insn" "mov,mvn,andor"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_e1_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (eq_attr "conds" "set")
        (eq_attr "insn" "mov,mvn,andor"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (not (eq_attr "conds" "set"))
        (not (eq_attr "insn" "mov,mvn,andor")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (eq_attr "conds" "set")
        (not (eq_attr "insn" "mov,mvn,andor")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
        (not (eq_attr "conds" "set"))
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
        (eq_attr "conds" "set")
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
        (not (eq_attr "conds" "set"))
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "conds" "set")
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_bypass 2 "pj4_alu_shift,pj4_shift"