From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19711 invoked by alias); 29 Oct 2010 19:48:42 -0000 Received: (qmail 19701 invoked by uid 22791); 29 Oct 2010 19:48:41 -0000 X-SWARE-Spam-Status: No, hits=-0.8 required=5.0 tests=AWL,BAYES_20,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from ausc60ps301.us.dell.com (HELO ausc60ps301.us.dell.com) (143.166.148.206) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 29 Oct 2010 19:48:35 +0000 X-Loopcount0: from 10.152.240.141 From: Paul Koning Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Subject: [PATCH] PR/41822 pdp11: fix wrong code for and operation Date: Fri, 29 Oct 2010 22:44:00 -0000 Message-Id: <68AF8014-024B-4FB6-B341-703AB7B17FB4@dell.com> To: gcc-patches Mime-Version: 1.0 (Apple Message framework v1081) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2010-10/txt/msg02589.txt.bz2 PDP11 has a bic instruction, which is and not. The code generation for tha= t was wrong. Fixed by borrowing, with changes, from vax.md. Tested by test build, inspection of generated assembly code. Committed. ChangeLog: 2010-10-29 Paul Koning PR/41822 * config/pdp11/pdp11.md (andhi3, andqi3): Fix wrong code error. Index: config/pdp11/pdp11.md =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- config/pdp11/pdp11.md (revision 166060) +++ config/pdp11/pdp11.md (working copy) @@ -43,6 +43,11 @@ ;; HI is 16 bit ;; QI is 8 bit=20 =20 +;; Integer modes supported on the PDP11, with a mapping from machine mode +;; to mnemonic suffix. SImode and DImode always are special cases. +(define_mode_iterator PDPint [QI HI]) +(define_mode_attr isfx [(QI "b") (HI "")]) + ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. =20 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code @@ -809,71 +814,41 @@ ;;;;- and instructions ;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn. =20 -(define_insn "andsi3" - [(set (match_operand:SI 0 "general_operand" "=3Dr,r,o,o,r,r,r,o,o,o") - (and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,= 0") - (not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J= ,K,I,J,K"))))] +(define_expand "and3" + [(set (match_operand:PDPint 0 "general_operand" "") + (and:PDPint (not:PDPint (match_operand:PDPint 1 "general_operand" "")) + (match_operand:PDPint 2 "general_operand" "")))] "" - "* -{ /* Here we trust that operands don't overlap=20 + " +{ + rtx op1 =3D operands[1]; =20 - or is lateoperands the low word?? - looks like it! */ + /* If there is a constant argument, complement that one. + Similarly, if one of the inputs is the same as the output, + complement the other input. */ + if ((CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) || + rtx_equal_p (operands[0], operands[1])) + { + operands[1] =3D operands[2]; + operands[2] =3D op1; + op1 =3D operands[1]; + } =20 - rtx lateoperands[3]; -=20=20 - lateoperands[0] =3D operands[0]; - - if (REG_P (operands[0])) - operands[0] =3D gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + if (CONST_INT_P (op1)) + operands[1] =3D GEN_INT (~INTVAL (op1)); else - operands[0] =3D adjust_address (operands[0], HImode, 2); -=20=20 - if (! CONSTANT_P(operands[2])) - { - lateoperands[2] =3D operands[2]; + operands[1] =3D expand_unop (mode, one_cmpl_optab, op1, 0, 1); +}") =20 - if (REG_P (operands[2])) - operands[2] =3D gen_rtx_REG (HImode, REGNO (operands[2]) + 1); - else - operands[2] =3D adjust_address (operands[2], HImode, 2); - - output_asm_insn (\"bic %2, %0\", operands); - output_asm_insn (\"bic %2, %0\", lateoperands); - return \"\"; - } - - lateoperands[2] =3D GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff); - operands[2] =3D GEN_INT (INTVAL (operands[2]) & 0xffff); -=20=20 - /* these have different lengths, so we should have=20 - different constraints! */ - if (INTVAL(operands[2])) - output_asm_insn (\"bic %2, %0\", operands); - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"bic %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "4,8,8,12,4,4,8,6,6,12")]) - -;; FIXME This definition is wrong, PR/41822 -(define_insn "andhi3" - [(set (match_operand:HI 0 "general_operand" "=3DrR,rR,Q,Q") - (and:HI (match_operand:HI 1 "general_operand" "0,0,0,0") - (not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))] +(define_insn "*and" + [(set (match_operand:PDPint 0 "general_operand" "=3DrR,rR,Q,Q") + (and:PDPint + (not: PDPint (match_operand:PDPint 1 "general_operand" "rR,Qi,rR,Qi"= )) + (match_operand:PDPint 2 "general_operand" "0,0,0,0")))] "" - "bic %2, %0" + "bic %1, %0" [(set_attr "length" "2,4,4,6")]) =20 -(define_insn "andqi3" - [(set (match_operand:QI 0 "general_operand" "=3DrR,rR,Q,Q") - (and:QI (match_operand:QI 1 "general_operand" "0,0,0,0") - (not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))] - "" - "bicb %2, %0" - [(set_attr "length" "2,4,4,6")]) - ;;- Bit set (inclusive or) instructions (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=3Dr,r,o,o,r,r,r,o,o,o")