Explicit sets multiple VNx1SImode with multiple dest operand and let RA to assign them with continguous regsiters
will make RTL patterns in RVV hard to maintain.

Assume we have a new pattern flag to tell RA assign continguous registers for multiple dest operand, and RA can handle this:
in RVV, we have NF = 2 ~ 8
Then we need to define RTL pattern for "vlseg" as follows:
NF = 2:
define_insn "vlseg2"
[(parallel_with_continguous_reg
  (set dest operand 0)
   (set dest operand 1)...])

NF = 3:
define_insn "vlseg3"
[(parallel_with_continguous_reg
  (set dest operand 0)
   (set dest operand 1)
    (set dest operand 2)...])
...


NF = 7:
define_insn "vlseg7"
[(parallel_with_continguous_reg
  (set dest operand 0)
   (set dest operand 1)
    (set dest operand 2)
(set dest operand 2)
(set dest operand 2)...])



juzhe.zhong@rivai.ai
 
From: Jakub Jelinek
Date: 2023-04-11 18:11
To: juzhe.zhong@rivai.ai
CC: jeffreyalaw; gcc-patches; kito.cheng; palmer; richard.sandiford; rguenther; Vladimir Makarov
Subject: Re: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit
On Tue, Apr 11, 2023 at 05:46:15PM +0800, juzhe.zhong@rivai.ai wrote:
> I am not sure whether aggregate type without a tuple mode can work for us.
> Here is the example:
> 
> We already had a vector type "vint8mf8_t", the corresponding mode is VNx1SImode.
> 
> Now we have an intrinsic as following:
> vint8mf8x2_t test_vlseg2e8_v_i8mf8(const int8_t *base, size_t vl) {
>   return __riscv_vlseg2e8_v_i8mf8(base, vl);
> }
> 
> This intrinsic is suppose generate a "vlseg2e8.v" instructions and dest operand of the intrinsic should be 2 continguous registers.
> 
> Another intrinsic:
>  vint8mf8x3_t test_vlseg3e8_v_i8mf8(const int8_t *base, size_t vl) {
>   return __riscv_vlseg3e8_v_i8mf8(base, vl);
> }
> 
> This intrinsic is suppose generate a "vlseg3e8.v" instructions and dest operand of the intrinsic should be 3 continguous registers.
> 
> Now, my plan is to build_array_type for both "vint8mf8x2_t" and "vint8mf8x3_t" and make their TYPE_MODE is "VNx2x1SI" and "VNx3x1SI" corresponding like ARM SVE.
> Then define the RTL pattern which has dest operand is a register_operand with mode  "VNx2x1SI" and "VNx3x1SI". Then we can do the codegen.
 
Another possibility would be just make it explicit in the RTL that it sets 3
VNx1SI mode REGs rather than one, as long as there is some way to tell RA
that they need to be consecutive.  CCing Vlad on that.
 
Jakub