Re: Re: [PATCH V3] RISC-V: Enable basic VLS modes support

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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>> Hmmm, does it mean we'll have (set (mem) (mem)) after legitimize_move???
The answer is yes. It's odd I know.

And I found the regression fail, for mem to mem pattern, I change it into:
(define_insn_and_split "*mov<mode>_mem_to_mem"
  [(set (match_operand:VLS_AVL_IMM 0 "memory_operand")
        (match_operand:VLS_AVL_IMM 1 "memory_operand"))]
  "TARGET_VECTOR && can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(const_int 0)]
  {
    if (GET_MODE_BITSIZE (<MODE>mode).to_constant () <= MAX_BITS_PER_WORD)
      {
        /* Opitmize the following case:

            typedef int8_t v2qi __attribute__ ((vector_size (2)));
            v2qi v = *(v2qi*)in;
            *(v2qi*)out = v;

            We prefer scalar load/store instead of vle.v/vse.v when
            the VLS modes size is smaller scalar mode.  */
        machine_mode mode;
        unsigned size = GET_MODE_BITSIZE (<MODE>mode).to_constant ();
        if (FLOAT_MODE_P (<MODE>mode))
          mode = mode_for_size (size, MODE_FLOAT, 0).require ();
        else
          mode = mode_for_size (size, MODE_INT, 0).require ();
        emit_move_insn (gen_lowpart (mode, operands[0]),
                        gen_lowpart (mode, operands[1]));
      }
    else
      {
        operands[1] = force_reg (<MODE>mode, operands[1]);
        emit_move_insn (operands[0], operands[1]);
      }
      DONE;
  }
)

Now regression passed....




juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-07-27 17:57
To: juzhe.zhong@rivai.ai
CC: gcc-patches; kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Enable basic VLS modes support
Hmmm, does it mean we'll have (set (mem) (mem)) after legitimize_move???
 
Or maybe try to
 
use define_insn_and_split rather than define_split for the (set (mem) (mem))
 
On Thu, Jul 27, 2023 at 5:50 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> Hi, kito.
> I tried to reject mem->mem in this pattern:
> (define_insn_and_split "*mov<mode>"
>   [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
>         (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" "  m,vr, vr"))]
>   "TARGET_VECTOR
>    && (register_operand (operands[0], <MODE>mode)
>        || register_operand (operands[1], <MODE>mode))"
>   "@
>    #
>    #
>    vmv%m1r.v\t%0,%1"
>   "&& reload_completed
>    && (!register_operand (operands[0], <MODE>mode)
>        || !register_operand (operands[1], <MODE>mode))"
>   [(const_int 0)]
>   {
>     bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
>     gcc_assert (ok_p);
>     DONE;
>   }
> )
>
>
> It cause ICE in regression during "vregs" (Before RA).
> [jzzhong@server1:/work/home/jzzhong/work/insn]$~/work/rvv-opensource/output/gcc-rv64/bin/riscv64-rivai-elf-gcc -march=rv64gc_zve32f -mabi=lp64d -O3 -S --param=riscv-autovec-preference=scalable -fdump-rtl-all auto.c
> auto.c: In function 'foo0':
> auto.c:15:1: error: unrecognizable insn:
>    15 | }
>       | ^
> (insn 35 34 36 6 (set (mem:V8QI (reg/f:DI 154 [ _64 ]) [0 MEM <vector(8) signed char> [(int8_t *)_64]+0 S8 A64])
>         (mem/u/c:V8QI (reg/f:DI 185) [0  S8 A64])) "auto.c":11:20 -1
>      (nil))
> during RTL pass: vregs
> dump file: auto.c.259r.vregs
>
>
> It seems that we need a placeholder pattern to hold mem->mem ?
>
> Could you help me with that ?
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-07-27 17:19
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Enable basic VLS modes support
> Last minor thing :)
>
> > +(define_insn_and_split "*mov<mode>"
> > +  [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> > +       (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" "  m,vr, vr"))]
> > +  "TARGET_VECTOR"
>
> Reject (set (mem) (mem)) by adding the check:
>
> TARGET_VECTOR
> && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
>     || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
>