Re: [PATCH] Remove CC0

["Koning, Paul" <Paul.Koning@dell.com>]

> On May 5, 2021, at 8:45 AM, Segher Boessenkool <segher@kernel.crashing.org> wrote:
> 
> Hi~
> 
> On Tue, May 04, 2021 at 04:08:22PM +0100, Richard Earnshaw wrote:
>> On 03/05/2021 23:55, Segher Boessenkool wrote:
>>> CC_STATUS_INIT is suggested in final.c to also be useful for ports that
>>> are not CC0, and at least arm seems to use it for something.  So I am
>>> leaving that alone, but most targets that have it could remove it.
>> 
>> A quick look through the code suggests it's being used for thumb1 code 
>> gen to try to reproduce the traditional CC0 type behaviour of 
>> eliminating redundant compare operations when you have sequences such as
>> 
>> cmp a, b
>> b<cond1> d1
>> cmp a, b
>> b<cond2> d2
>> 
>> The second compare operation can be eliminated.
>> 
>> It might be possible to eliminate this another way by reworking the 
>> thumb1 codegen to expose the condition codes after register allocation 
>> has completed (much like x86 does these days), but that would be quite a 
>> lot of work right now.  I don't know if such splitting would directly 
>> lead to the ability to remove the redundant compares - it might need a 
>> new pass to spot them.
> 
> At least on rs6000 on a simple example this is handled by fwprop1
> already.  Does that work for thumb1?  Or maybe that uses hard regs for
> the condition codes and that does not work here?
> 
> Example code:
> 
> ===
> void g(void);
> void h(void);
> void i(void);
> void f(long a, long b)
> {
>        if (a < b)
>                g();
>        if (a == b)
>                h();
>        if (a > b)
>                i();
> }

FWIW, that also works on pdp11, so it seems the general mechanism is in place and working.  Well, with one oddity, an unnecessary third conditional branch:

_f:
	mov	02(sp),r1
	mov	04(sp),r0
	cmp	r1,r0
	blt	L_7
	beq	L_4
	bgt	L_5
	rts	pc
L_5:
	jsr	pc,_i
	rts	pc
L_4:
	jsr	pc,_h
	rts	pc
L_7:
	jsr	pc,_g
	rts	pc