From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25808 invoked by alias); 7 Feb 2017 14:09:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25737 invoked by uid 89); 7 Feb 2017 14:09:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=sk:hard_re, sk:lra_get, hard_regno, dfmode X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 07 Feb 2017 14:08:51 +0000 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id A9080B62C4C07; Tue, 7 Feb 2017 14:08:45 +0000 (GMT) Received: from HHMAIL-X.hh.imgtec.org (10.100.10.113) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 7 Feb 2017 14:08:48 +0000 Received: from hhmail02.hh.imgtec.org ([fe80::5400:d33e:81a4:f775]) by HHMAIL-X.hh.imgtec.org ([fe80::3509:b0ce:371:2b%18]) with mapi id 14.03.0294.000; Tue, 7 Feb 2017 14:08:48 +0000 From: Matthew Fortune To: "'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)" CC: Vladimir Makarov , "Eric Botcazou (ebotcazou@adacore.com)" , Robert Suchanek , "Moore, Catherine (Catherine_Moore@mentor.com)" Subject: [PATCH 5/5] Ensure the mode used to create split registers is suppported Date: Tue, 07 Feb 2017 14:09:00 -0000 Message-ID: <6D39441BF12EF246A7ABCE6654B0235380B5CE9A@hhmail02.hh.imgtec.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-IsSubscribed: yes X-SW-Source: 2017-02/txt/msg00521.txt.bz2 Hi, This patch addresses a problem with LRA splitting hard registers where the mode requires multiple registers. When splitting then each constituent register is split individually using the widest mode for each register but no check is made that such a mode is actually supported in those registers. MIPS has an ABI variant o32 FPXX that allows DFmode values to exist in pairs of 32-bit floating point registers but only the first 32-bit register is directly addressable. The second register can only be accessed as part of a 64-bit load/store or via a special move instruction used as part of a 64-bit move. The split is simply rejected to ensure compliance with the ABI although I expect the split logic could account for this case and split using the wider mode. Such a change appears more invasive than appropriate in stage 4. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D78012 It is unknown if any other LRA enabled target could hit this issue but it is certainly possible depending on mode/register restrictions. Thanks, Matthew Author: Robert Suchanek gcc/ PR target/78012 * lra-constraints.c (split_reg): Check requested split mode is supported by the register. --- gcc/lra-constraints.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index 0b7ae34..db6e878 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -5402,6 +5402,26 @@ split_reg (bool before_p, int original_regno, rtx_in= sn *insn, } return false; } + /* Split_if_necessary can split hard registers used as part of a + multi-register mode but splits each register individually. The + mode used for each independent register may not be supported + so reject the split. Splitting the wider mode should theoretically + be possible but is not implemented. */ + if (! HARD_REGNO_MODE_OK (hard_regno, mode)) + { + if (lra_dump_file !=3D NULL) + { + fprintf (lra_dump_file, + " Rejecting split of %d(%s): unsuitable mode %s\n", + original_regno, + reg_class_names[lra_get_allocno_class (original_regno)], + GET_MODE_NAME (mode)); + fprintf + (lra_dump_file, + " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); + } + return false; + } new_reg =3D lra_create_new_reg (mode, original_reg, rclass, "split"); reg_renumber[REGNO (new_reg)] =3D hard_regno; } --=20 2.2.1