* [PATCH 2/2] RISC-V: Refactor vector reduction patterns
@ 2023-09-13 12:31 Lehua Ding
2023-09-14 14:10 ` 钟居哲
0 siblings, 1 reply; 4+ messages in thread
From: Lehua Ding @ 2023-09-13 12:31 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, kito.cheng, rdapp.gcc, palmer, jeffreyalaw, lehua.ding
This patch adjust reduction patterns struct, change it from:
(any_reduc:VI
(vec_duplicate:VI
(vec_select:<VEL>
(match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
(match_operand:VI 3 "register_operand" " vr, vr"))
to:
(unspec:<V_LMUL1> [
(match_operand:VI 3 "register_operand" " vr, vr")
(match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
] ANY_REDUC)
The reason for the change is that the semantics of the previous pattern is incorrect.
GCC does not have a standard rtx code to express the reduction calculation process.
It makes more sense to use UNSPEC.
Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)),
so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop
and widen_freducop are redundant.
gcc/ChangeLog:
* config/riscv/autovec.md: Change rtx code to unspec.
* config/riscv/riscv-protos.h (expand_reduction): Change prototype.
* config/riscv/riscv-v.cc (expand_reduction): Change prototype.
* config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
Removed.
(class widen_freducop): Removed.
* config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
* config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name.
(@pred_<reduc_op><mode>): New name.
(@pred_widen_reduc_plus<v_su><mode>): Change name.
(@pred_reduc_plus<order><mode>): Change name.
(@pred_widen_reduc_plus<order><mode>): Change name.
---
gcc/config/riscv/autovec.md | 27 ++--
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 82 ++++--------
gcc/config/riscv/vector-iterators.md | 62 +++++++--
gcc/config/riscv/vector.md | 118 +++++++++---------
6 files changed, 152 insertions(+), 152 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4a6b8f8c939..16ac125f53f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2091,7 +2091,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2102,7 +2102,7 @@
{
int prec = GET_MODE_PRECISION (<VEL>mode);
rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), <VEL>mode);
- riscv_vector::expand_reduction (SMAX, operands, min);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
DONE;
})
@@ -2111,7 +2111,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2122,7 +2122,7 @@
{
int prec = GET_MODE_PRECISION (<VEL>mode);
rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), <VEL>mode);
- riscv_vector::expand_reduction (SMIN, operands, max);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
DONE;
})
@@ -2133,7 +2133,7 @@
{
int prec = GET_MODE_PRECISION (<VEL>mode);
rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), <VEL>mode);
- riscv_vector::expand_reduction (UMIN, operands, max);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
DONE;
})
@@ -2142,7 +2142,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX (<VEL>mode));
DONE;
})
@@ -2151,7 +2151,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2160,7 +2160,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2178,7 +2178,8 @@
(match_operand:VF 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
+ CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2190,7 +2191,7 @@
REAL_VALUE_TYPE rv;
real_inf (&rv, true);
rtx f = const_double_from_real_value (rv, <VEL>mode);
- riscv_vector::expand_reduction (SMAX, operands, f);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, f);
DONE;
})
@@ -2202,7 +2203,7 @@
REAL_VALUE_TYPE rv;
real_inf (&rv, false);
rtx f = const_double_from_real_value (rv, <VEL>mode);
- riscv_vector::expand_reduction (SMIN, operands, f);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, f);
DONE;
})
@@ -2220,7 +2221,7 @@
(match_operand:VF 2 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (PLUS, operands,
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
operands[1],
riscv_vector::reduction_type::FOLD_LEFT);
DONE;
@@ -2239,7 +2240,7 @@
if (rtx_equal_p (operands[4], const0_rtx))
emit_move_insn (operands[0], operands[1]);
else
- riscv_vector::expand_reduction (PLUS, operands,
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
operands[1],
riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
DONE;
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index d08d5dfeef4..44fa36c32ab 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -433,7 +433,7 @@ void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
void expand_cond_len_unop (unsigned, rtx *);
void expand_cond_len_binop (unsigned, rtx *);
-void expand_reduction (rtx_code, rtx *, rtx,
+void expand_reduction (unsigned, rtx *, rtx,
reduction_type = reduction_type::UNORDERED);
#endif
bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 68b36d9dc4f..1bf5471beaf 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3208,7 +3208,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
/* Expand reduction operations. */
void
-expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
+expand_reduction (unsigned unspec, rtx *ops, rtx init, reduction_type type)
{
rtx vector = type == reduction_type::UNORDERED ? ops[1] : ops[2];
machine_mode vmode = GET_MODE (vector);
@@ -3224,13 +3224,10 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
rtx m1_tmp2 = gen_reg_rtx (m1_mode);
rtx reduc_ops[] = {m1_tmp2, vector, m1_tmp};
- if (FLOAT_MODE_P (vmode) && code == PLUS)
+ if (unspec == UNSPEC_REDUC_SUM_ORDERED
+ || unspec == UNSPEC_REDUC_SUM_UNORDERED)
{
- insn_code icode
- = code_for_pred_reduc_plus (type == reduction_type::UNORDERED
- ? UNSPEC_UNORDERED
- : UNSPEC_ORDERED,
- vmode);
+ insn_code icode = code_for_pred (unspec, vmode);
if (type == reduction_type::MASK_LEN_FOLD_LEFT)
{
rtx mask = ops[3];
@@ -3243,7 +3240,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
}
else
{
- insn_code icode = code_for_pred_reduc (code, vmode);
+ insn_code icode = code_for_pred (unspec, vmode);
emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
}
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c54ea6f0560..ab12e130907 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1533,7 +1533,7 @@ public:
};
/* Implements reduction instructions. */
-template<rtx_code CODE>
+template<unsigned UNSPEC>
class reducop : public function_base
{
public:
@@ -1541,26 +1541,12 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ()));
- }
-};
-
-/* Implements widen reduction instructions. */
-template<int UNSPEC>
-class widen_reducop : public function_base
-{
-public:
- bool apply_mask_policy_p () const override { return false; }
-
- rtx expand (function_expander &e) const override
- {
- return e.use_exact_insn (
- code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
+ return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
}
};
/* Implements floating-point reduction instructions. */
-template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM >
+template<unsigned UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
class freducop : public function_base
{
public:
@@ -1573,27 +1559,7 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (
- code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
- }
-};
-
-/* Implements widening floating-point reduction instructions. */
-template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
-class widen_freducop : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override
- {
- return FRM_OP == HAS_FRM;
- }
-
- bool apply_mask_policy_p () const override { return false; }
-
- rtx expand (function_expander &e) const override
- {
- return e.use_exact_insn (
- code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
+ return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
}
};
@@ -2281,26 +2247,26 @@ static CONSTEXPR const vfncvt_rtz_x<UNSIGNED_FIX> vfncvt_rtz_xu_obj;
static CONSTEXPR const vfncvt_f<NO_FRM> vfncvt_f_obj;
static CONSTEXPR const vfncvt_f<HAS_FRM> vfncvt_f_frm_obj;
static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj;
-static CONSTEXPR const reducop<PLUS> vredsum_obj;
-static CONSTEXPR const reducop<UMAX> vredmaxu_obj;
-static CONSTEXPR const reducop<SMAX> vredmax_obj;
-static CONSTEXPR const reducop<UMIN> vredminu_obj;
-static CONSTEXPR const reducop<SMIN> vredmin_obj;
-static CONSTEXPR const reducop<AND> vredand_obj;
-static CONSTEXPR const reducop<IOR> vredor_obj;
-static CONSTEXPR const reducop<XOR> vredxor_obj;
-static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
-static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_USUM> vwredsumu_obj;
-static CONSTEXPR const freducop<UNSPEC_UNORDERED> vfredusum_obj;
-static CONSTEXPR const freducop<UNSPEC_UNORDERED, HAS_FRM> vfredusum_frm_obj;
-static CONSTEXPR const freducop<UNSPEC_ORDERED> vfredosum_obj;
-static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj;
-static CONSTEXPR const reducop<SMAX> vfredmax_obj;
-static CONSTEXPR const reducop<SMIN> vfredmin_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_SUM> vredsum_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MAXU> vredmaxu_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vredmax_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MINU> vredminu_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vredmin_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_AND> vredand_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_OR> vredor_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_XOR> vredxor_obj;
+static CONSTEXPR const reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
+static CONSTEXPR const reducop<UNSPEC_WREDUC_SUMU> vwredsumu_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED> vfredusum_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED, HAS_FRM> vfredusum_frm_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED> vfredosum_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED, HAS_FRM> vfredosum_frm_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vfredmax_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vfredmin_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED> vfwredusum_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED> vfwredosum_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED, HAS_FRM> vfwredosum_frm_obj;
static CONSTEXPR const vmv vmv_x_obj;
static CONSTEXPR const vmv_s vmv_s_obj;
static CONSTEXPR const vmv vfmv_f_obj;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index deb89cbcedc..c9d0a501910 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -67,9 +67,6 @@
UNSPEC_UNSIGNED_VFCVT
UNSPEC_ROD
- UNSPEC_REDUC
- UNSPEC_WREDUC_SUM
- UNSPEC_WREDUC_USUM
UNSPEC_VSLIDEUP
UNSPEC_VSLIDEDOWN
UNSPEC_VSLIDE1UP
@@ -83,6 +80,24 @@
UNSPEC_MODIFY_VL
UNSPEC_VFFMA
+
+ ;; Integer and Float Reduction
+ UNSPEC_REDUC
+ UNSPEC_REDUC_SUM
+ UNSPEC_REDUC_SUM_ORDERED
+ UNSPEC_REDUC_SUM_UNORDERED
+ UNSPEC_REDUC_MAXU
+ UNSPEC_REDUC_MAX
+ UNSPEC_REDUC_MINU
+ UNSPEC_REDUC_MIN
+ UNSPEC_REDUC_AND
+ UNSPEC_REDUC_OR
+ UNSPEC_REDUC_XOR
+
+ UNSPEC_WREDUC_SUM
+ UNSPEC_WREDUC_SUMU
+ UNSPEC_WREDUC_SUM_ORDERED
+ UNSPEC_WREDUC_SUM_UNORDERED
])
(define_c_enum "unspecv" [
@@ -1274,6 +1289,36 @@
(RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
])
+(define_int_iterator ANY_REDUC [
+ UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU
+ UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
+])
+
+(define_int_iterator ANY_WREDUC [
+ UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
+])
+
+(define_int_iterator ANY_FREDUC [
+ UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
+])
+
+(define_int_iterator ANY_FREDUC_SUM [
+ UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
+])
+
+(define_int_iterator ANY_FWREDUC_SUM [
+ UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
+])
+
+(define_int_attr reduc_op [
+ (UNSPEC_REDUC_SUM "redsum")
+ (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
+ (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
+ (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor")
+ (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
+ (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum")
+])
+
(define_mode_attr VINDEX [
(RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI")
(RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI")
@@ -2271,8 +2316,6 @@
(RVVM2DF "vector_gs_scale_operand_64") (RVVM1DF "vector_gs_scale_operand_64")
])
-(define_int_iterator WREDUC [UNSPEC_WREDUC_SUM UNSPEC_WREDUC_USUM])
-
(define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
(define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU])
@@ -2301,12 +2344,13 @@
(define_int_attr order [
(UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
+ (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
+ (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
])
(define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su")
(UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
- (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")
- (UNSPEC_WREDUC_SUM "") (UNSPEC_WREDUC_USUM "u")])
+ (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")])
(define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
(UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
(UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
@@ -2392,10 +2436,6 @@
(define_code_iterator any_fix [fix unsigned_fix])
(define_code_iterator any_float [float unsigned_float])
-(define_code_iterator any_reduc [plus umax smax umin smin and ior xor])
-(define_code_iterator any_freduc [smax smin])
-(define_code_attr reduc [(plus "sum") (umax "maxu") (smax "max") (umin "minu")
- (smin "min") (and "and") (ior "or") (xor "xor")])
(define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")])
(define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index b6c8e63b0b2..3dd54509315 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7726,7 +7726,7 @@
;; -------------------------------------------------------------------------------
;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
-(define_insn "@pred_reduc_<reduc><mode>"
+(define_insn "@pred_<reduc_op><mode>"
[(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
(unspec:<V_LMUL1>
[(unspec:<VM>
@@ -7736,39 +7736,39 @@
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VI
- (vec_duplicate:VI
- (vec_select:<VEL>
- (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VI 3 "register_operand" " vr, vr"))
+ (unspec:<V_LMUL1> [
+ (match_operand:VI 3 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_REDUC)
(match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vred<reduc>.vs\t%0,%3,%4%p1"
+ "v<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<MODE>")])
-;; Integer Reduction Sum Widen (vwredsum[u].vs)
-(define_insn "@pred_widen_reduc_plus<v_su><mode>"
- [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
+;; Integer Widen Reduction Sum (vwredsum[u].vs)
+(define_insn "@pred_<reduc_op><mode>"
+ [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VI_QHS 3 "register_operand" " vr, vr")
- (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
- (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] WREDUC))]
+ (unspec:<V_EXT_LMUL1> [
+ (match_operand:VI_QHS 3 "register_operand" " vr, vr")
+ (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_WREDUC)
+ (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vwredsum<v_su>.vs\t%0,%3,%4%p1"
+ "v<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "viwred")
(set_attr "mode" "<MODE>")])
;; Float Reduction (vfred(max|min).vs)
-(define_insn "@pred_reduc_<reduc><mode>"
+(define_insn "@pred_<reduc_op><mode>"
[(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
(unspec:<V_LMUL1>
[(unspec:<VM>
@@ -7778,65 +7778,61 @@
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_freduc:VF
- (vec_duplicate:VF
- (vec_select:<VEL>
- (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VF 3 "register_operand" " vr, vr"))
+ (unspec:<V_LMUL1> [
+ (match_operand:VF 3 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_FREDUC)
(match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vfred<reduc>.vs\t%0,%3,%4%p1"
+ "vf<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
-;; Float Ordered Reduction Sum (vfred[ou]sum.vs)
-(define_insn "@pred_reduc_plus<order><mode>"
+;; Float Reduction Sum (vfred[ou]sum.vs)
+(define_insn "@pred_<reduc_op><mode>"
[(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
(unspec:<V_LMUL1>
- [(unspec:<V_LMUL1>
- [(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VF
- (vec_duplicate:VF
- (vec_select:<VEL>
- (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VF 3 "register_operand" " vr, vr"))
- (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<V_LMUL1> [
+ (match_operand:VF 3 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_FREDUC_SUM)
+ (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vfred<order>sum.vs\t%0,%3,%4%p1"
+ "vf<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
-(define_insn "@pred_widen_reduc_plus<order><mode>"
- [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
+(define_insn "@pred_<reduc_op><mode>"
+ [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
(unspec:<V_EXT_LMUL1>
- [(unspec:<V_EXT_LMUL1>
- [(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<V_EXT_LMUL1> [
(match_operand:VF_HS 3 "register_operand" " vr, vr")
(match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
- (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
+ ] ANY_FWREDUC_SUM)
+ (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vfwred<order>sum.vs\t%0,%3,%4%p1"
+ "vf<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
2023-09-13 12:31 [PATCH 2/2] RISC-V: Refactor vector reduction patterns Lehua Ding
@ 2023-09-14 14:10 ` 钟居哲
2023-09-14 14:53 ` Kito Cheng
0 siblings, 1 reply; 4+ messages in thread
From: 钟居哲 @ 2023-09-14 14:10 UTC (permalink / raw)
To: 丁乐华, gcc-patches
Cc: kito.cheng, rdapp.gcc, palmer, Jeff Law, 丁乐华
[-- Attachment #1: Type: text/plain, Size: 26297 bytes --]
LGTM.
It's obvious you fixed my previous redundant codes.
Thanks.
juzhe.zhong@rivai.ai
From: Lehua Ding
Date: 2023-09-13 20:31
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
This patch adjust reduction patterns struct, change it from:
(any_reduc:VI
(vec_duplicate:VI
(vec_select:<VEL>
(match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
(match_operand:VI 3 "register_operand" " vr, vr"))
to:
(unspec:<V_LMUL1> [
(match_operand:VI 3 "register_operand" " vr, vr")
(match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
] ANY_REDUC)
The reason for the change is that the semantics of the previous pattern is incorrect.
GCC does not have a standard rtx code to express the reduction calculation process.
It makes more sense to use UNSPEC.
Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)),
so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop
and widen_freducop are redundant.
gcc/ChangeLog:
* config/riscv/autovec.md: Change rtx code to unspec.
* config/riscv/riscv-protos.h (expand_reduction): Change prototype.
* config/riscv/riscv-v.cc (expand_reduction): Change prototype.
* config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
Removed.
(class widen_freducop): Removed.
* config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
* config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name.
(@pred_<reduc_op><mode>): New name.
(@pred_widen_reduc_plus<v_su><mode>): Change name.
(@pred_reduc_plus<order><mode>): Change name.
(@pred_widen_reduc_plus<order><mode>): Change name.
---
gcc/config/riscv/autovec.md | 27 ++--
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 82 ++++--------
gcc/config/riscv/vector-iterators.md | 62 +++++++--
gcc/config/riscv/vector.md | 118 +++++++++---------
6 files changed, 152 insertions(+), 152 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4a6b8f8c939..16ac125f53f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2091,7 +2091,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2102,7 +2102,7 @@
{
int prec = GET_MODE_PRECISION (<VEL>mode);
rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), <VEL>mode);
- riscv_vector::expand_reduction (SMAX, operands, min);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
DONE;
})
@@ -2111,7 +2111,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2122,7 +2122,7 @@
{
int prec = GET_MODE_PRECISION (<VEL>mode);
rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), <VEL>mode);
- riscv_vector::expand_reduction (SMIN, operands, max);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
DONE;
})
@@ -2133,7 +2133,7 @@
{
int prec = GET_MODE_PRECISION (<VEL>mode);
rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), <VEL>mode);
- riscv_vector::expand_reduction (UMIN, operands, max);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
DONE;
})
@@ -2142,7 +2142,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX (<VEL>mode));
DONE;
})
@@ -2151,7 +2151,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2160,7 +2160,7 @@
(match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2178,7 +2178,8 @@
(match_operand:VF 1 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
+ CONST0_RTX (<VEL>mode));
DONE;
})
@@ -2190,7 +2191,7 @@
REAL_VALUE_TYPE rv;
real_inf (&rv, true);
rtx f = const_double_from_real_value (rv, <VEL>mode);
- riscv_vector::expand_reduction (SMAX, operands, f);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, f);
DONE;
})
@@ -2202,7 +2203,7 @@
REAL_VALUE_TYPE rv;
real_inf (&rv, false);
rtx f = const_double_from_real_value (rv, <VEL>mode);
- riscv_vector::expand_reduction (SMIN, operands, f);
+ riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, f);
DONE;
})
@@ -2220,7 +2221,7 @@
(match_operand:VF 2 "register_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_reduction (PLUS, operands,
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
operands[1],
riscv_vector::reduction_type::FOLD_LEFT);
DONE;
@@ -2239,7 +2240,7 @@
if (rtx_equal_p (operands[4], const0_rtx))
emit_move_insn (operands[0], operands[1]);
else
- riscv_vector::expand_reduction (PLUS, operands,
+ riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
operands[1],
riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
DONE;
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index d08d5dfeef4..44fa36c32ab 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -433,7 +433,7 @@ void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
void expand_cond_len_unop (unsigned, rtx *);
void expand_cond_len_binop (unsigned, rtx *);
-void expand_reduction (rtx_code, rtx *, rtx,
+void expand_reduction (unsigned, rtx *, rtx,
reduction_type = reduction_type::UNORDERED);
#endif
bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 68b36d9dc4f..1bf5471beaf 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3208,7 +3208,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
/* Expand reduction operations. */
void
-expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
+expand_reduction (unsigned unspec, rtx *ops, rtx init, reduction_type type)
{
rtx vector = type == reduction_type::UNORDERED ? ops[1] : ops[2];
machine_mode vmode = GET_MODE (vector);
@@ -3224,13 +3224,10 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
rtx m1_tmp2 = gen_reg_rtx (m1_mode);
rtx reduc_ops[] = {m1_tmp2, vector, m1_tmp};
- if (FLOAT_MODE_P (vmode) && code == PLUS)
+ if (unspec == UNSPEC_REDUC_SUM_ORDERED
+ || unspec == UNSPEC_REDUC_SUM_UNORDERED)
{
- insn_code icode
- = code_for_pred_reduc_plus (type == reduction_type::UNORDERED
- ? UNSPEC_UNORDERED
- : UNSPEC_ORDERED,
- vmode);
+ insn_code icode = code_for_pred (unspec, vmode);
if (type == reduction_type::MASK_LEN_FOLD_LEFT)
{
rtx mask = ops[3];
@@ -3243,7 +3240,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
}
else
{
- insn_code icode = code_for_pred_reduc (code, vmode);
+ insn_code icode = code_for_pred (unspec, vmode);
emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
}
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c54ea6f0560..ab12e130907 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1533,7 +1533,7 @@ public:
};
/* Implements reduction instructions. */
-template<rtx_code CODE>
+template<unsigned UNSPEC>
class reducop : public function_base
{
public:
@@ -1541,26 +1541,12 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ()));
- }
-};
-
-/* Implements widen reduction instructions. */
-template<int UNSPEC>
-class widen_reducop : public function_base
-{
-public:
- bool apply_mask_policy_p () const override { return false; }
-
- rtx expand (function_expander &e) const override
- {
- return e.use_exact_insn (
- code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
+ return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
}
};
/* Implements floating-point reduction instructions. */
-template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM >
+template<unsigned UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
class freducop : public function_base
{
public:
@@ -1573,27 +1559,7 @@ public:
rtx expand (function_expander &e) const override
{
- return e.use_exact_insn (
- code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
- }
-};
-
-/* Implements widening floating-point reduction instructions. */
-template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
-class widen_freducop : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override
- {
- return FRM_OP == HAS_FRM;
- }
-
- bool apply_mask_policy_p () const override { return false; }
-
- rtx expand (function_expander &e) const override
- {
- return e.use_exact_insn (
- code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
+ return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
}
};
@@ -2281,26 +2247,26 @@ static CONSTEXPR const vfncvt_rtz_x<UNSIGNED_FIX> vfncvt_rtz_xu_obj;
static CONSTEXPR const vfncvt_f<NO_FRM> vfncvt_f_obj;
static CONSTEXPR const vfncvt_f<HAS_FRM> vfncvt_f_frm_obj;
static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj;
-static CONSTEXPR const reducop<PLUS> vredsum_obj;
-static CONSTEXPR const reducop<UMAX> vredmaxu_obj;
-static CONSTEXPR const reducop<SMAX> vredmax_obj;
-static CONSTEXPR const reducop<UMIN> vredminu_obj;
-static CONSTEXPR const reducop<SMIN> vredmin_obj;
-static CONSTEXPR const reducop<AND> vredand_obj;
-static CONSTEXPR const reducop<IOR> vredor_obj;
-static CONSTEXPR const reducop<XOR> vredxor_obj;
-static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
-static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_USUM> vwredsumu_obj;
-static CONSTEXPR const freducop<UNSPEC_UNORDERED> vfredusum_obj;
-static CONSTEXPR const freducop<UNSPEC_UNORDERED, HAS_FRM> vfredusum_frm_obj;
-static CONSTEXPR const freducop<UNSPEC_ORDERED> vfredosum_obj;
-static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj;
-static CONSTEXPR const reducop<SMAX> vfredmax_obj;
-static CONSTEXPR const reducop<SMIN> vfredmin_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj;
-static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_SUM> vredsum_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MAXU> vredmaxu_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vredmax_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MINU> vredminu_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vredmin_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_AND> vredand_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_OR> vredor_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_XOR> vredxor_obj;
+static CONSTEXPR const reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
+static CONSTEXPR const reducop<UNSPEC_WREDUC_SUMU> vwredsumu_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED> vfredusum_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED, HAS_FRM> vfredusum_frm_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED> vfredosum_obj;
+static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED, HAS_FRM> vfredosum_frm_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vfredmax_obj;
+static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vfredmin_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED> vfwredusum_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED> vfwredosum_obj;
+static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED, HAS_FRM> vfwredosum_frm_obj;
static CONSTEXPR const vmv vmv_x_obj;
static CONSTEXPR const vmv_s vmv_s_obj;
static CONSTEXPR const vmv vfmv_f_obj;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index deb89cbcedc..c9d0a501910 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -67,9 +67,6 @@
UNSPEC_UNSIGNED_VFCVT
UNSPEC_ROD
- UNSPEC_REDUC
- UNSPEC_WREDUC_SUM
- UNSPEC_WREDUC_USUM
UNSPEC_VSLIDEUP
UNSPEC_VSLIDEDOWN
UNSPEC_VSLIDE1UP
@@ -83,6 +80,24 @@
UNSPEC_MODIFY_VL
UNSPEC_VFFMA
+
+ ;; Integer and Float Reduction
+ UNSPEC_REDUC
+ UNSPEC_REDUC_SUM
+ UNSPEC_REDUC_SUM_ORDERED
+ UNSPEC_REDUC_SUM_UNORDERED
+ UNSPEC_REDUC_MAXU
+ UNSPEC_REDUC_MAX
+ UNSPEC_REDUC_MINU
+ UNSPEC_REDUC_MIN
+ UNSPEC_REDUC_AND
+ UNSPEC_REDUC_OR
+ UNSPEC_REDUC_XOR
+
+ UNSPEC_WREDUC_SUM
+ UNSPEC_WREDUC_SUMU
+ UNSPEC_WREDUC_SUM_ORDERED
+ UNSPEC_WREDUC_SUM_UNORDERED
])
(define_c_enum "unspecv" [
@@ -1274,6 +1289,36 @@
(RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
])
+(define_int_iterator ANY_REDUC [
+ UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU
+ UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
+])
+
+(define_int_iterator ANY_WREDUC [
+ UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
+])
+
+(define_int_iterator ANY_FREDUC [
+ UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
+])
+
+(define_int_iterator ANY_FREDUC_SUM [
+ UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
+])
+
+(define_int_iterator ANY_FWREDUC_SUM [
+ UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
+])
+
+(define_int_attr reduc_op [
+ (UNSPEC_REDUC_SUM "redsum")
+ (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
+ (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
+ (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor")
+ (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
+ (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum")
+])
+
(define_mode_attr VINDEX [
(RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI")
(RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI")
@@ -2271,8 +2316,6 @@
(RVVM2DF "vector_gs_scale_operand_64") (RVVM1DF "vector_gs_scale_operand_64")
])
-(define_int_iterator WREDUC [UNSPEC_WREDUC_SUM UNSPEC_WREDUC_USUM])
-
(define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
(define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU])
@@ -2301,12 +2344,13 @@
(define_int_attr order [
(UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
+ (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
+ (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
])
(define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su")
(UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
- (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")
- (UNSPEC_WREDUC_SUM "") (UNSPEC_WREDUC_USUM "u")])
+ (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")])
(define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
(UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
(UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
@@ -2392,10 +2436,6 @@
(define_code_iterator any_fix [fix unsigned_fix])
(define_code_iterator any_float [float unsigned_float])
-(define_code_iterator any_reduc [plus umax smax umin smin and ior xor])
-(define_code_iterator any_freduc [smax smin])
-(define_code_attr reduc [(plus "sum") (umax "maxu") (smax "max") (umin "minu")
- (smin "min") (and "and") (ior "or") (xor "xor")])
(define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")])
(define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index b6c8e63b0b2..3dd54509315 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7726,7 +7726,7 @@
;; -------------------------------------------------------------------------------
;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
-(define_insn "@pred_reduc_<reduc><mode>"
+(define_insn "@pred_<reduc_op><mode>"
[(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
(unspec:<V_LMUL1>
[(unspec:<VM>
@@ -7736,39 +7736,39 @@
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_reduc:VI
- (vec_duplicate:VI
- (vec_select:<VEL>
- (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VI 3 "register_operand" " vr, vr"))
+ (unspec:<V_LMUL1> [
+ (match_operand:VI 3 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_REDUC)
(match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vred<reduc>.vs\t%0,%3,%4%p1"
+ "v<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<MODE>")])
-;; Integer Reduction Sum Widen (vwredsum[u].vs)
-(define_insn "@pred_widen_reduc_plus<v_su><mode>"
- [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
+;; Integer Widen Reduction Sum (vwredsum[u].vs)
+(define_insn "@pred_<reduc_op><mode>"
+ [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operand:VI_QHS 3 "register_operand" " vr, vr")
- (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
- (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] WREDUC))]
+ (unspec:<V_EXT_LMUL1> [
+ (match_operand:VI_QHS 3 "register_operand" " vr, vr")
+ (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_WREDUC)
+ (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vwredsum<v_su>.vs\t%0,%3,%4%p1"
+ "v<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "viwred")
(set_attr "mode" "<MODE>")])
;; Float Reduction (vfred(max|min).vs)
-(define_insn "@pred_reduc_<reduc><mode>"
+(define_insn "@pred_<reduc_op><mode>"
[(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
(unspec:<V_LMUL1>
[(unspec:<VM>
@@ -7778,65 +7778,61 @@
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_freduc:VF
- (vec_duplicate:VF
- (vec_select:<VEL>
- (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VF 3 "register_operand" " vr, vr"))
+ (unspec:<V_LMUL1> [
+ (match_operand:VF 3 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_FREDUC)
(match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vfred<reduc>.vs\t%0,%3,%4%p1"
+ "vf<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
-;; Float Ordered Reduction Sum (vfred[ou]sum.vs)
-(define_insn "@pred_reduc_plus<order><mode>"
+;; Float Reduction Sum (vfred[ou]sum.vs)
+(define_insn "@pred_<reduc_op><mode>"
[(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
(unspec:<V_LMUL1>
- [(unspec:<V_LMUL1>
- [(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (plus:VF
- (vec_duplicate:VF
- (vec_select:<VEL>
- (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
- (parallel [(const_int 0)])))
- (match_operand:VF 3 "register_operand" " vr, vr"))
- (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<V_LMUL1> [
+ (match_operand:VF 3 "register_operand" " vr, vr")
+ (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
+ ] ANY_FREDUC_SUM)
+ (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vfred<order>sum.vs\t%0,%3,%4%p1"
+ "vf<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
-(define_insn "@pred_widen_reduc_plus<order><mode>"
- [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
+(define_insn "@pred_<reduc_op><mode>"
+ [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
(unspec:<V_EXT_LMUL1>
- [(unspec:<V_EXT_LMUL1>
- [(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ [(unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<V_EXT_LMUL1> [
(match_operand:VF_HS 3 "register_operand" " vr, vr")
(match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
- (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
+ ] ANY_FWREDUC_SUM)
+ (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR"
- "vfwred<order>sum.vs\t%0,%3,%4%p1"
+ "vf<reduc_op>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
2023-09-14 14:10 ` 钟居哲
@ 2023-09-14 14:53 ` Kito Cheng
2023-09-14 15:01 ` Lehua Ding
0 siblings, 1 reply; 4+ messages in thread
From: Kito Cheng @ 2023-09-14 14:53 UTC (permalink / raw)
To: 钟居哲
Cc: 丁乐华, gcc-patches, rdapp.gcc, palmer, Jeff Law
LGTM too :)
On Thu, Sep 14, 2023 at 10:11 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
> It's obvious you fixed my previous redundant codes.
> Thanks.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Lehua Ding
> Date: 2023-09-13 20:31
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
> Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
> This patch adjust reduction patterns struct, change it from:
> (any_reduc:VI
> (vec_duplicate:VI
> (vec_select:<VEL>
> (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> (parallel [(const_int 0)])))
> (match_operand:VI 3 "register_operand" " vr, vr"))
> to:
> (unspec:<V_LMUL1> [
> (match_operand:VI 3 "register_operand" " vr, vr")
> (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> ] ANY_REDUC)
>
> The reason for the change is that the semantics of the previous pattern is incorrect.
> GCC does not have a standard rtx code to express the reduction calculation process.
> It makes more sense to use UNSPEC.
>
> Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)),
> so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop
> and widen_freducop are redundant.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Change rtx code to unspec.
> * config/riscv/riscv-protos.h (expand_reduction): Change prototype.
> * config/riscv/riscv-v.cc (expand_reduction): Change prototype.
> * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
> Removed.
> (class widen_freducop): Removed.
> * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
> * config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name.
> (@pred_<reduc_op><mode>): New name.
> (@pred_widen_reduc_plus<v_su><mode>): Change name.
> (@pred_reduc_plus<order><mode>): Change name.
> (@pred_widen_reduc_plus<order><mode>): Change name.
>
> ---
> gcc/config/riscv/autovec.md | 27 ++--
> gcc/config/riscv/riscv-protos.h | 2 +-
> gcc/config/riscv/riscv-v.cc | 13 +-
> .../riscv/riscv-vector-builtins-bases.cc | 82 ++++--------
> gcc/config/riscv/vector-iterators.md | 62 +++++++--
> gcc/config/riscv/vector.md | 118 +++++++++---------
> 6 files changed, 152 insertions(+), 152 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 4a6b8f8c939..16ac125f53f 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2091,7 +2091,7 @@
> (match_operand:VI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2102,7 +2102,7 @@
> {
> int prec = GET_MODE_PRECISION (<VEL>mode);
> rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), <VEL>mode);
> - riscv_vector::expand_reduction (SMAX, operands, min);
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
> DONE;
> })
> @@ -2111,7 +2111,7 @@
> (match_operand:VI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (<VEL>mode));
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2122,7 +2122,7 @@
> {
> int prec = GET_MODE_PRECISION (<VEL>mode);
> rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), <VEL>mode);
> - riscv_vector::expand_reduction (SMIN, operands, max);
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
> DONE;
> })
> @@ -2133,7 +2133,7 @@
> {
> int prec = GET_MODE_PRECISION (<VEL>mode);
> rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), <VEL>mode);
> - riscv_vector::expand_reduction (UMIN, operands, max);
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
> DONE;
> })
> @@ -2142,7 +2142,7 @@
> (match_operand:VI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (<VEL>mode));
> + riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX (<VEL>mode));
> DONE;
> })
> @@ -2151,7 +2151,7 @@
> (match_operand:VI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (<VEL>mode));
> + riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2160,7 +2160,7 @@
> (match_operand:VI 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (<VEL>mode));
> + riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2178,7 +2178,8 @@
> (match_operand:VF 1 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
> + CONST0_RTX (<VEL>mode));
> DONE;
> })
> @@ -2190,7 +2191,7 @@
> REAL_VALUE_TYPE rv;
> real_inf (&rv, true);
> rtx f = const_double_from_real_value (rv, <VEL>mode);
> - riscv_vector::expand_reduction (SMAX, operands, f);
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, f);
> DONE;
> })
> @@ -2202,7 +2203,7 @@
> REAL_VALUE_TYPE rv;
> real_inf (&rv, false);
> rtx f = const_double_from_real_value (rv, <VEL>mode);
> - riscv_vector::expand_reduction (SMIN, operands, f);
> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, f);
> DONE;
> })
> @@ -2220,7 +2221,7 @@
> (match_operand:VF 2 "register_operand")]
> "TARGET_VECTOR"
> {
> - riscv_vector::expand_reduction (PLUS, operands,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
> operands[1],
> riscv_vector::reduction_type::FOLD_LEFT);
> DONE;
> @@ -2239,7 +2240,7 @@
> if (rtx_equal_p (operands[4], const0_rtx))
> emit_move_insn (operands[0], operands[1]);
> else
> - riscv_vector::expand_reduction (PLUS, operands,
> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
> operands[1],
> riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
> DONE;
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index d08d5dfeef4..44fa36c32ab 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -433,7 +433,7 @@ void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
> bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
> void expand_cond_len_unop (unsigned, rtx *);
> void expand_cond_len_binop (unsigned, rtx *);
> -void expand_reduction (rtx_code, rtx *, rtx,
> +void expand_reduction (unsigned, rtx *, rtx,
> reduction_type = reduction_type::UNORDERED);
> #endif
> bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 68b36d9dc4f..1bf5471beaf 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -3208,7 +3208,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
> /* Expand reduction operations. */
> void
> -expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
> +expand_reduction (unsigned unspec, rtx *ops, rtx init, reduction_type type)
> {
> rtx vector = type == reduction_type::UNORDERED ? ops[1] : ops[2];
> machine_mode vmode = GET_MODE (vector);
> @@ -3224,13 +3224,10 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
> rtx m1_tmp2 = gen_reg_rtx (m1_mode);
> rtx reduc_ops[] = {m1_tmp2, vector, m1_tmp};
> - if (FLOAT_MODE_P (vmode) && code == PLUS)
> + if (unspec == UNSPEC_REDUC_SUM_ORDERED
> + || unspec == UNSPEC_REDUC_SUM_UNORDERED)
> {
> - insn_code icode
> - = code_for_pred_reduc_plus (type == reduction_type::UNORDERED
> - ? UNSPEC_UNORDERED
> - : UNSPEC_ORDERED,
> - vmode);
> + insn_code icode = code_for_pred (unspec, vmode);
> if (type == reduction_type::MASK_LEN_FOLD_LEFT)
> {
> rtx mask = ops[3];
> @@ -3243,7 +3240,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
> }
> else
> {
> - insn_code icode = code_for_pred_reduc (code, vmode);
> + insn_code icode = code_for_pred (unspec, vmode);
> emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
> }
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index c54ea6f0560..ab12e130907 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1533,7 +1533,7 @@ public:
> };
> /* Implements reduction instructions. */
> -template<rtx_code CODE>
> +template<unsigned UNSPEC>
> class reducop : public function_base
> {
> public:
> @@ -1541,26 +1541,12 @@ public:
> rtx expand (function_expander &e) const override
> {
> - return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ()));
> - }
> -};
> -
> -/* Implements widen reduction instructions. */
> -template<int UNSPEC>
> -class widen_reducop : public function_base
> -{
> -public:
> - bool apply_mask_policy_p () const override { return false; }
> -
> - rtx expand (function_expander &e) const override
> - {
> - return e.use_exact_insn (
> - code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
> + return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
> }
> };
> /* Implements floating-point reduction instructions. */
> -template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM >
> +template<unsigned UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
> class freducop : public function_base
> {
> public:
> @@ -1573,27 +1559,7 @@ public:
> rtx expand (function_expander &e) const override
> {
> - return e.use_exact_insn (
> - code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
> - }
> -};
> -
> -/* Implements widening floating-point reduction instructions. */
> -template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
> -class widen_freducop : public function_base
> -{
> -public:
> - bool has_rounding_mode_operand_p () const override
> - {
> - return FRM_OP == HAS_FRM;
> - }
> -
> - bool apply_mask_policy_p () const override { return false; }
> -
> - rtx expand (function_expander &e) const override
> - {
> - return e.use_exact_insn (
> - code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
> + return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
> }
> };
> @@ -2281,26 +2247,26 @@ static CONSTEXPR const vfncvt_rtz_x<UNSIGNED_FIX> vfncvt_rtz_xu_obj;
> static CONSTEXPR const vfncvt_f<NO_FRM> vfncvt_f_obj;
> static CONSTEXPR const vfncvt_f<HAS_FRM> vfncvt_f_frm_obj;
> static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj;
> -static CONSTEXPR const reducop<PLUS> vredsum_obj;
> -static CONSTEXPR const reducop<UMAX> vredmaxu_obj;
> -static CONSTEXPR const reducop<SMAX> vredmax_obj;
> -static CONSTEXPR const reducop<UMIN> vredminu_obj;
> -static CONSTEXPR const reducop<SMIN> vredmin_obj;
> -static CONSTEXPR const reducop<AND> vredand_obj;
> -static CONSTEXPR const reducop<IOR> vredor_obj;
> -static CONSTEXPR const reducop<XOR> vredxor_obj;
> -static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
> -static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_USUM> vwredsumu_obj;
> -static CONSTEXPR const freducop<UNSPEC_UNORDERED> vfredusum_obj;
> -static CONSTEXPR const freducop<UNSPEC_UNORDERED, HAS_FRM> vfredusum_frm_obj;
> -static CONSTEXPR const freducop<UNSPEC_ORDERED> vfredosum_obj;
> -static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj;
> -static CONSTEXPR const reducop<SMAX> vfredmax_obj;
> -static CONSTEXPR const reducop<SMIN> vfredmin_obj;
> -static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj;
> -static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
> -static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj;
> -static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_SUM> vredsum_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_MAXU> vredmaxu_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vredmax_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_MINU> vredminu_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vredmin_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_AND> vredand_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_OR> vredor_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_XOR> vredxor_obj;
> +static CONSTEXPR const reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
> +static CONSTEXPR const reducop<UNSPEC_WREDUC_SUMU> vwredsumu_obj;
> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED> vfredusum_obj;
> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED, HAS_FRM> vfredusum_frm_obj;
> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED> vfredosum_obj;
> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED, HAS_FRM> vfredosum_frm_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vfredmax_obj;
> +static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vfredmin_obj;
> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED> vfwredusum_obj;
> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED> vfwredosum_obj;
> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED, HAS_FRM> vfwredosum_frm_obj;
> static CONSTEXPR const vmv vmv_x_obj;
> static CONSTEXPR const vmv_s vmv_s_obj;
> static CONSTEXPR const vmv vfmv_f_obj;
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index deb89cbcedc..c9d0a501910 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -67,9 +67,6 @@
> UNSPEC_UNSIGNED_VFCVT
> UNSPEC_ROD
> - UNSPEC_REDUC
> - UNSPEC_WREDUC_SUM
> - UNSPEC_WREDUC_USUM
> UNSPEC_VSLIDEUP
> UNSPEC_VSLIDEDOWN
> UNSPEC_VSLIDE1UP
> @@ -83,6 +80,24 @@
> UNSPEC_MODIFY_VL
> UNSPEC_VFFMA
> +
> + ;; Integer and Float Reduction
> + UNSPEC_REDUC
> + UNSPEC_REDUC_SUM
> + UNSPEC_REDUC_SUM_ORDERED
> + UNSPEC_REDUC_SUM_UNORDERED
> + UNSPEC_REDUC_MAXU
> + UNSPEC_REDUC_MAX
> + UNSPEC_REDUC_MINU
> + UNSPEC_REDUC_MIN
> + UNSPEC_REDUC_AND
> + UNSPEC_REDUC_OR
> + UNSPEC_REDUC_XOR
> +
> + UNSPEC_WREDUC_SUM
> + UNSPEC_WREDUC_SUMU
> + UNSPEC_WREDUC_SUM_ORDERED
> + UNSPEC_WREDUC_SUM_UNORDERED
> ])
> (define_c_enum "unspecv" [
> @@ -1274,6 +1289,36 @@
> (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
> ])
> +(define_int_iterator ANY_REDUC [
> + UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU
> + UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
> +])
> +
> +(define_int_iterator ANY_WREDUC [
> + UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
> +])
> +
> +(define_int_iterator ANY_FREDUC [
> + UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
> +])
> +
> +(define_int_iterator ANY_FREDUC_SUM [
> + UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
> +])
> +
> +(define_int_iterator ANY_FWREDUC_SUM [
> + UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
> +])
> +
> +(define_int_attr reduc_op [
> + (UNSPEC_REDUC_SUM "redsum")
> + (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
> + (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
> + (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor")
> + (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
> + (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum")
> +])
> +
> (define_mode_attr VINDEX [
> (RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI")
> (RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI")
> @@ -2271,8 +2316,6 @@
> (RVVM2DF "vector_gs_scale_operand_64") (RVVM1DF "vector_gs_scale_operand_64")
> ])
> -(define_int_iterator WREDUC [UNSPEC_WREDUC_SUM UNSPEC_WREDUC_USUM])
> -
> (define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
> (define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU])
> @@ -2301,12 +2344,13 @@
> (define_int_attr order [
> (UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
> + (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
> + (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
> ])
> (define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su")
> (UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
> - (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")
> - (UNSPEC_WREDUC_SUM "") (UNSPEC_WREDUC_USUM "u")])
> + (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")])
> (define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
> (UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
> (UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
> @@ -2392,10 +2436,6 @@
> (define_code_iterator any_fix [fix unsigned_fix])
> (define_code_iterator any_float [float unsigned_float])
> -(define_code_iterator any_reduc [plus umax smax umin smin and ior xor])
> -(define_code_iterator any_freduc [smax smin])
> -(define_code_attr reduc [(plus "sum") (umax "maxu") (smax "max") (umin "minu")
> - (smin "min") (and "and") (ior "or") (xor "xor")])
> (define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")])
> (define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")])
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index b6c8e63b0b2..3dd54509315 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -7726,7 +7726,7 @@
> ;; -------------------------------------------------------------------------------
> ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
> -(define_insn "@pred_reduc_<reduc><mode>"
> +(define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
> (unspec:<V_LMUL1>
> [(unspec:<VM>
> @@ -7736,39 +7736,39 @@
> (match_operand 7 "const_int_operand" " i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (any_reduc:VI
> - (vec_duplicate:VI
> - (vec_select:<VEL>
> - (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> - (parallel [(const_int 0)])))
> - (match_operand:VI 3 "register_operand" " vr, vr"))
> + (unspec:<V_LMUL1> [
> + (match_operand:VI 3 "register_operand" " vr, vr")
> + (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> + ] ANY_REDUC)
> (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> "TARGET_VECTOR"
> - "vred<reduc>.vs\t%0,%3,%4%p1"
> + "v<reduc_op>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vired")
> (set_attr "mode" "<MODE>")])
> -;; Integer Reduction Sum Widen (vwredsum[u].vs)
> -(define_insn "@pred_widen_reduc_plus<v_su><mode>"
> - [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
> +;; Integer Widen Reduction Sum (vwredsum[u].vs)
> +(define_insn "@pred_<reduc_op><mode>"
> + [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
> (unspec:<V_EXT_LMUL1>
> [(unspec:<VM>
> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
> - (match_operand 5 "vector_length_operand" " rK, rK")
> - (match_operand 6 "const_int_operand" " i, i")
> - (match_operand 7 "const_int_operand" " i, i")
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
> + (match_operand 5 "vector_length_operand" " rK, rK")
> + (match_operand 6 "const_int_operand" " i, i")
> + (match_operand 7 "const_int_operand" " i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (match_operand:VI_QHS 3 "register_operand" " vr, vr")
> - (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
> - (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] WREDUC))]
> + (unspec:<V_EXT_LMUL1> [
> + (match_operand:VI_QHS 3 "register_operand" " vr, vr")
> + (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
> + ] ANY_WREDUC)
> + (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> "TARGET_VECTOR"
> - "vwredsum<v_su>.vs\t%0,%3,%4%p1"
> + "v<reduc_op>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "viwred")
> (set_attr "mode" "<MODE>")])
> ;; Float Reduction (vfred(max|min).vs)
> -(define_insn "@pred_reduc_<reduc><mode>"
> +(define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
> (unspec:<V_LMUL1>
> [(unspec:<VM>
> @@ -7778,65 +7778,61 @@
> (match_operand 7 "const_int_operand" " i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (any_freduc:VF
> - (vec_duplicate:VF
> - (vec_select:<VEL>
> - (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> - (parallel [(const_int 0)])))
> - (match_operand:VF 3 "register_operand" " vr, vr"))
> + (unspec:<V_LMUL1> [
> + (match_operand:VF 3 "register_operand" " vr, vr")
> + (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> + ] ANY_FREDUC)
> (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> "TARGET_VECTOR"
> - "vfred<reduc>.vs\t%0,%3,%4%p1"
> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> -;; Float Ordered Reduction Sum (vfred[ou]sum.vs)
> -(define_insn "@pred_reduc_plus<order><mode>"
> +;; Float Reduction Sum (vfred[ou]sum.vs)
> +(define_insn "@pred_<reduc_op><mode>"
> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
> (unspec:<V_LMUL1>
> - [(unspec:<V_LMUL1>
> - [(unspec:<VM>
> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
> - (match_operand 5 "vector_length_operand" " rK, rK")
> - (match_operand 6 "const_int_operand" " i, i")
> - (match_operand 7 "const_int_operand" " i, i")
> - (match_operand 8 "const_int_operand" " i, i")
> - (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> - (plus:VF
> - (vec_duplicate:VF
> - (vec_select:<VEL>
> - (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> - (parallel [(const_int 0)])))
> - (match_operand:VF 3 "register_operand" " vr, vr"))
> - (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
> + (match_operand 5 "vector_length_operand" " rK, rK")
> + (match_operand 6 "const_int_operand" " i, i")
> + (match_operand 7 "const_int_operand" " i, i")
> + (match_operand 8 "const_int_operand" " i, i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_LMUL1> [
> + (match_operand:VF 3 "register_operand" " vr, vr")
> + (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
> + ] ANY_FREDUC_SUM)
> + (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> "TARGET_VECTOR"
> - "vfred<order>sum.vs\t%0,%3,%4%p1"
> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")
> (set (attr "frm_mode")
> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
> ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
> -(define_insn "@pred_widen_reduc_plus<order><mode>"
> - [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
> +(define_insn "@pred_<reduc_op><mode>"
> + [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
> (unspec:<V_EXT_LMUL1>
> - [(unspec:<V_EXT_LMUL1>
> - [(unspec:<VM>
> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
> - (match_operand 5 "vector_length_operand" " rK, rK")
> - (match_operand 6 "const_int_operand" " i, i")
> - (match_operand 7 "const_int_operand" " i, i")
> - (match_operand 8 "const_int_operand" " i, i")
> - (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)
> - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> + [(unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
> + (match_operand 5 "vector_length_operand" " rK, rK")
> + (match_operand 6 "const_int_operand" " i, i")
> + (match_operand 7 "const_int_operand" " i, i")
> + (match_operand 8 "const_int_operand" " i, i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> + (unspec:<V_EXT_LMUL1> [
> (match_operand:VF_HS 3 "register_operand" " vr, vr")
> (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
> - (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> + ] ANY_FWREDUC_SUM)
> + (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> "TARGET_VECTOR"
> - "vfwred<order>sum.vs\t%0,%3,%4%p1"
> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")
> (set (attr "frm_mode")
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
2023-09-14 14:53 ` Kito Cheng
@ 2023-09-14 15:01 ` Lehua Ding
0 siblings, 0 replies; 4+ messages in thread
From: Lehua Ding @ 2023-09-14 15:01 UTC (permalink / raw)
To: Kito Cheng, 钟居哲
Cc: gcc-patches, rdapp.gcc, palmer, Jeff Law
Committed, thanks Kito and Juzhe.
On 2023/9/14 22:53, Kito Cheng wrote:
> LGTM too :)
>
> On Thu, Sep 14, 2023 at 10:11 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>>
>> LGTM.
>> It's obvious you fixed my previous redundant codes.
>> Thanks.
>>
>>
>>
>> juzhe.zhong@rivai.ai
>>
>> From: Lehua Ding
>> Date: 2023-09-13 20:31
>> To: gcc-patches
>> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
>> Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
>> This patch adjust reduction patterns struct, change it from:
>> (any_reduc:VI
>> (vec_duplicate:VI
>> (vec_select:<VEL>
>> (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> (parallel [(const_int 0)])))
>> (match_operand:VI 3 "register_operand" " vr, vr"))
>> to:
>> (unspec:<V_LMUL1> [
>> (match_operand:VI 3 "register_operand" " vr, vr")
>> (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> ] ANY_REDUC)
>>
>> The reason for the change is that the semantics of the previous pattern is incorrect.
>> GCC does not have a standard rtx code to express the reduction calculation process.
>> It makes more sense to use UNSPEC.
>>
>> Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)),
>> so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop
>> and widen_freducop are redundant.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/autovec.md: Change rtx code to unspec.
>> * config/riscv/riscv-protos.h (expand_reduction): Change prototype.
>> * config/riscv/riscv-v.cc (expand_reduction): Change prototype.
>> * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
>> Removed.
>> (class widen_freducop): Removed.
>> * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
>> * config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name.
>> (@pred_<reduc_op><mode>): New name.
>> (@pred_widen_reduc_plus<v_su><mode>): Change name.
>> (@pred_reduc_plus<order><mode>): Change name.
>> (@pred_widen_reduc_plus<order><mode>): Change name.
>>
>> ---
>> gcc/config/riscv/autovec.md | 27 ++--
>> gcc/config/riscv/riscv-protos.h | 2 +-
>> gcc/config/riscv/riscv-v.cc | 13 +-
>> .../riscv/riscv-vector-builtins-bases.cc | 82 ++++--------
>> gcc/config/riscv/vector-iterators.md | 62 +++++++--
>> gcc/config/riscv/vector.md | 118 +++++++++---------
>> 6 files changed, 152 insertions(+), 152 deletions(-)
>>
>> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
>> index 4a6b8f8c939..16ac125f53f 100644
>> --- a/gcc/config/riscv/autovec.md
>> +++ b/gcc/config/riscv/autovec.md
>> @@ -2091,7 +2091,7 @@
>> (match_operand:VI 1 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (<VEL>mode));
>> DONE;
>> })
>> @@ -2102,7 +2102,7 @@
>> {
>> int prec = GET_MODE_PRECISION (<VEL>mode);
>> rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), <VEL>mode);
>> - riscv_vector::expand_reduction (SMAX, operands, min);
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
>> DONE;
>> })
>> @@ -2111,7 +2111,7 @@
>> (match_operand:VI 1 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (<VEL>mode));
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX (<VEL>mode));
>> DONE;
>> })
>> @@ -2122,7 +2122,7 @@
>> {
>> int prec = GET_MODE_PRECISION (<VEL>mode);
>> rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), <VEL>mode);
>> - riscv_vector::expand_reduction (SMIN, operands, max);
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
>> DONE;
>> })
>> @@ -2133,7 +2133,7 @@
>> {
>> int prec = GET_MODE_PRECISION (<VEL>mode);
>> rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), <VEL>mode);
>> - riscv_vector::expand_reduction (UMIN, operands, max);
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
>> DONE;
>> })
>> @@ -2142,7 +2142,7 @@
>> (match_operand:VI 1 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (<VEL>mode));
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX (<VEL>mode));
>> DONE;
>> })
>> @@ -2151,7 +2151,7 @@
>> (match_operand:VI 1 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (<VEL>mode));
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX (<VEL>mode));
>> DONE;
>> })
>> @@ -2160,7 +2160,7 @@
>> (match_operand:VI 1 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (<VEL>mode));
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX (<VEL>mode));
>> DONE;
>> })
>> @@ -2178,7 +2178,8 @@
>> (match_operand:VF 1 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (<VEL>mode));
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
>> + CONST0_RTX (<VEL>mode));
>> DONE;
>> })
>> @@ -2190,7 +2191,7 @@
>> REAL_VALUE_TYPE rv;
>> real_inf (&rv, true);
>> rtx f = const_double_from_real_value (rv, <VEL>mode);
>> - riscv_vector::expand_reduction (SMAX, operands, f);
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, f);
>> DONE;
>> })
>> @@ -2202,7 +2203,7 @@
>> REAL_VALUE_TYPE rv;
>> real_inf (&rv, false);
>> rtx f = const_double_from_real_value (rv, <VEL>mode);
>> - riscv_vector::expand_reduction (SMIN, operands, f);
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, f);
>> DONE;
>> })
>> @@ -2220,7 +2221,7 @@
>> (match_operand:VF 2 "register_operand")]
>> "TARGET_VECTOR"
>> {
>> - riscv_vector::expand_reduction (PLUS, operands,
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
>> operands[1],
>> riscv_vector::reduction_type::FOLD_LEFT);
>> DONE;
>> @@ -2239,7 +2240,7 @@
>> if (rtx_equal_p (operands[4], const0_rtx))
>> emit_move_insn (operands[0], operands[1]);
>> else
>> - riscv_vector::expand_reduction (PLUS, operands,
>> + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
>> operands[1],
>> riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
>> DONE;
>> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
>> index d08d5dfeef4..44fa36c32ab 100644
>> --- a/gcc/config/riscv/riscv-protos.h
>> +++ b/gcc/config/riscv/riscv-protos.h
>> @@ -433,7 +433,7 @@ void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
>> bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
>> void expand_cond_len_unop (unsigned, rtx *);
>> void expand_cond_len_binop (unsigned, rtx *);
>> -void expand_reduction (rtx_code, rtx *, rtx,
>> +void expand_reduction (unsigned, rtx *, rtx,
>> reduction_type = reduction_type::UNORDERED);
>> #endif
>> bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
>> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
>> index 68b36d9dc4f..1bf5471beaf 100644
>> --- a/gcc/config/riscv/riscv-v.cc
>> +++ b/gcc/config/riscv/riscv-v.cc
>> @@ -3208,7 +3208,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
>> /* Expand reduction operations. */
>> void
>> -expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
>> +expand_reduction (unsigned unspec, rtx *ops, rtx init, reduction_type type)
>> {
>> rtx vector = type == reduction_type::UNORDERED ? ops[1] : ops[2];
>> machine_mode vmode = GET_MODE (vector);
>> @@ -3224,13 +3224,10 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
>> rtx m1_tmp2 = gen_reg_rtx (m1_mode);
>> rtx reduc_ops[] = {m1_tmp2, vector, m1_tmp};
>> - if (FLOAT_MODE_P (vmode) && code == PLUS)
>> + if (unspec == UNSPEC_REDUC_SUM_ORDERED
>> + || unspec == UNSPEC_REDUC_SUM_UNORDERED)
>> {
>> - insn_code icode
>> - = code_for_pred_reduc_plus (type == reduction_type::UNORDERED
>> - ? UNSPEC_UNORDERED
>> - : UNSPEC_ORDERED,
>> - vmode);
>> + insn_code icode = code_for_pred (unspec, vmode);
>> if (type == reduction_type::MASK_LEN_FOLD_LEFT)
>> {
>> rtx mask = ops[3];
>> @@ -3243,7 +3240,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type)
>> }
>> else
>> {
>> - insn_code icode = code_for_pred_reduc (code, vmode);
>> + insn_code icode = code_for_pred (unspec, vmode);
>> emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
>> }
>> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> index c54ea6f0560..ab12e130907 100644
>> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> @@ -1533,7 +1533,7 @@ public:
>> };
>> /* Implements reduction instructions. */
>> -template<rtx_code CODE>
>> +template<unsigned UNSPEC>
>> class reducop : public function_base
>> {
>> public:
>> @@ -1541,26 +1541,12 @@ public:
>> rtx expand (function_expander &e) const override
>> {
>> - return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ()));
>> - }
>> -};
>> -
>> -/* Implements widen reduction instructions. */
>> -template<int UNSPEC>
>> -class widen_reducop : public function_base
>> -{
>> -public:
>> - bool apply_mask_policy_p () const override { return false; }
>> -
>> - rtx expand (function_expander &e) const override
>> - {
>> - return e.use_exact_insn (
>> - code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
>> + return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
>> }
>> };
>> /* Implements floating-point reduction instructions. */
>> -template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM >
>> +template<unsigned UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
>> class freducop : public function_base
>> {
>> public:
>> @@ -1573,27 +1559,7 @@ public:
>> rtx expand (function_expander &e) const override
>> {
>> - return e.use_exact_insn (
>> - code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
>> - }
>> -};
>> -
>> -/* Implements widening floating-point reduction instructions. */
>> -template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
>> -class widen_freducop : public function_base
>> -{
>> -public:
>> - bool has_rounding_mode_operand_p () const override
>> - {
>> - return FRM_OP == HAS_FRM;
>> - }
>> -
>> - bool apply_mask_policy_p () const override { return false; }
>> -
>> - rtx expand (function_expander &e) const override
>> - {
>> - return e.use_exact_insn (
>> - code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
>> + return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
>> }
>> };
>> @@ -2281,26 +2247,26 @@ static CONSTEXPR const vfncvt_rtz_x<UNSIGNED_FIX> vfncvt_rtz_xu_obj;
>> static CONSTEXPR const vfncvt_f<NO_FRM> vfncvt_f_obj;
>> static CONSTEXPR const vfncvt_f<HAS_FRM> vfncvt_f_frm_obj;
>> static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj;
>> -static CONSTEXPR const reducop<PLUS> vredsum_obj;
>> -static CONSTEXPR const reducop<UMAX> vredmaxu_obj;
>> -static CONSTEXPR const reducop<SMAX> vredmax_obj;
>> -static CONSTEXPR const reducop<UMIN> vredminu_obj;
>> -static CONSTEXPR const reducop<SMIN> vredmin_obj;
>> -static CONSTEXPR const reducop<AND> vredand_obj;
>> -static CONSTEXPR const reducop<IOR> vredor_obj;
>> -static CONSTEXPR const reducop<XOR> vredxor_obj;
>> -static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
>> -static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_USUM> vwredsumu_obj;
>> -static CONSTEXPR const freducop<UNSPEC_UNORDERED> vfredusum_obj;
>> -static CONSTEXPR const freducop<UNSPEC_UNORDERED, HAS_FRM> vfredusum_frm_obj;
>> -static CONSTEXPR const freducop<UNSPEC_ORDERED> vfredosum_obj;
>> -static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj;
>> -static CONSTEXPR const reducop<SMAX> vfredmax_obj;
>> -static CONSTEXPR const reducop<SMIN> vfredmin_obj;
>> -static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj;
>> -static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
>> -static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj;
>> -static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_SUM> vredsum_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_MAXU> vredmaxu_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vredmax_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_MINU> vredminu_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vredmin_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_AND> vredand_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_OR> vredor_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_XOR> vredxor_obj;
>> +static CONSTEXPR const reducop<UNSPEC_WREDUC_SUM> vwredsum_obj;
>> +static CONSTEXPR const reducop<UNSPEC_WREDUC_SUMU> vwredsumu_obj;
>> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED> vfredusum_obj;
>> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_UNORDERED, HAS_FRM> vfredusum_frm_obj;
>> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED> vfredosum_obj;
>> +static CONSTEXPR const freducop<UNSPEC_REDUC_SUM_ORDERED, HAS_FRM> vfredosum_frm_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_MAX> vfredmax_obj;
>> +static CONSTEXPR const reducop<UNSPEC_REDUC_MIN> vfredmin_obj;
>> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED> vfwredusum_obj;
>> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
>> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED> vfwredosum_obj;
>> +static CONSTEXPR const freducop<UNSPEC_WREDUC_SUM_ORDERED, HAS_FRM> vfwredosum_frm_obj;
>> static CONSTEXPR const vmv vmv_x_obj;
>> static CONSTEXPR const vmv_s vmv_s_obj;
>> static CONSTEXPR const vmv vfmv_f_obj;
>> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
>> index deb89cbcedc..c9d0a501910 100644
>> --- a/gcc/config/riscv/vector-iterators.md
>> +++ b/gcc/config/riscv/vector-iterators.md
>> @@ -67,9 +67,6 @@
>> UNSPEC_UNSIGNED_VFCVT
>> UNSPEC_ROD
>> - UNSPEC_REDUC
>> - UNSPEC_WREDUC_SUM
>> - UNSPEC_WREDUC_USUM
>> UNSPEC_VSLIDEUP
>> UNSPEC_VSLIDEDOWN
>> UNSPEC_VSLIDE1UP
>> @@ -83,6 +80,24 @@
>> UNSPEC_MODIFY_VL
>> UNSPEC_VFFMA
>> +
>> + ;; Integer and Float Reduction
>> + UNSPEC_REDUC
>> + UNSPEC_REDUC_SUM
>> + UNSPEC_REDUC_SUM_ORDERED
>> + UNSPEC_REDUC_SUM_UNORDERED
>> + UNSPEC_REDUC_MAXU
>> + UNSPEC_REDUC_MAX
>> + UNSPEC_REDUC_MINU
>> + UNSPEC_REDUC_MIN
>> + UNSPEC_REDUC_AND
>> + UNSPEC_REDUC_OR
>> + UNSPEC_REDUC_XOR
>> +
>> + UNSPEC_WREDUC_SUM
>> + UNSPEC_WREDUC_SUMU
>> + UNSPEC_WREDUC_SUM_ORDERED
>> + UNSPEC_WREDUC_SUM_UNORDERED
>> ])
>> (define_c_enum "unspecv" [
>> @@ -1274,6 +1289,36 @@
>> (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
>> ])
>> +(define_int_iterator ANY_REDUC [
>> + UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU
>> + UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
>> +])
>> +
>> +(define_int_iterator ANY_WREDUC [
>> + UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
>> +])
>> +
>> +(define_int_iterator ANY_FREDUC [
>> + UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
>> +])
>> +
>> +(define_int_iterator ANY_FREDUC_SUM [
>> + UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
>> +])
>> +
>> +(define_int_iterator ANY_FWREDUC_SUM [
>> + UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
>> +])
>> +
>> +(define_int_attr reduc_op [
>> + (UNSPEC_REDUC_SUM "redsum")
>> + (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
>> + (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
>> + (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor")
>> + (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
>> + (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum")
>> +])
>> +
>> (define_mode_attr VINDEX [
>> (RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI")
>> (RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI")
>> @@ -2271,8 +2316,6 @@
>> (RVVM2DF "vector_gs_scale_operand_64") (RVVM1DF "vector_gs_scale_operand_64")
>> ])
>> -(define_int_iterator WREDUC [UNSPEC_WREDUC_SUM UNSPEC_WREDUC_USUM])
>> -
>> (define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
>> (define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU])
>> @@ -2301,12 +2344,13 @@
>> (define_int_attr order [
>> (UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
>> + (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
>> + (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
>> ])
>> (define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su")
>> (UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
>> - (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")
>> - (UNSPEC_WREDUC_SUM "") (UNSPEC_WREDUC_USUM "u")])
>> + (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")])
>> (define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
>> (UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
>> (UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
>> @@ -2392,10 +2436,6 @@
>> (define_code_iterator any_fix [fix unsigned_fix])
>> (define_code_iterator any_float [float unsigned_float])
>> -(define_code_iterator any_reduc [plus umax smax umin smin and ior xor])
>> -(define_code_iterator any_freduc [smax smin])
>> -(define_code_attr reduc [(plus "sum") (umax "maxu") (smax "max") (umin "minu")
>> - (smin "min") (and "and") (ior "or") (xor "xor")])
>> (define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")])
>> (define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")])
>> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
>> index b6c8e63b0b2..3dd54509315 100644
>> --- a/gcc/config/riscv/vector.md
>> +++ b/gcc/config/riscv/vector.md
>> @@ -7726,7 +7726,7 @@
>> ;; -------------------------------------------------------------------------------
>> ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
>> -(define_insn "@pred_reduc_<reduc><mode>"
>> +(define_insn "@pred_<reduc_op><mode>"
>> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
>> (unspec:<V_LMUL1>
>> [(unspec:<VM>
>> @@ -7736,39 +7736,39 @@
>> (match_operand 7 "const_int_operand" " i, i")
>> (reg:SI VL_REGNUM)
>> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>> - (any_reduc:VI
>> - (vec_duplicate:VI
>> - (vec_select:<VEL>
>> - (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> - (parallel [(const_int 0)])))
>> - (match_operand:VI 3 "register_operand" " vr, vr"))
>> + (unspec:<V_LMUL1> [
>> + (match_operand:VI 3 "register_operand" " vr, vr")
>> + (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> + ] ANY_REDUC)
>> (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
>> "TARGET_VECTOR"
>> - "vred<reduc>.vs\t%0,%3,%4%p1"
>> + "v<reduc_op>.vs\t%0,%3,%4%p1"
>> [(set_attr "type" "vired")
>> (set_attr "mode" "<MODE>")])
>> -;; Integer Reduction Sum Widen (vwredsum[u].vs)
>> -(define_insn "@pred_widen_reduc_plus<v_su><mode>"
>> - [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
>> +;; Integer Widen Reduction Sum (vwredsum[u].vs)
>> +(define_insn "@pred_<reduc_op><mode>"
>> + [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
>> (unspec:<V_EXT_LMUL1>
>> [(unspec:<VM>
>> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
>> - (match_operand 5 "vector_length_operand" " rK, rK")
>> - (match_operand 6 "const_int_operand" " i, i")
>> - (match_operand 7 "const_int_operand" " i, i")
>> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
>> + (match_operand 5 "vector_length_operand" " rK, rK")
>> + (match_operand 6 "const_int_operand" " i, i")
>> + (match_operand 7 "const_int_operand" " i, i")
>> (reg:SI VL_REGNUM)
>> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>> - (match_operand:VI_QHS 3 "register_operand" " vr, vr")
>> - (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
>> - (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] WREDUC))]
>> + (unspec:<V_EXT_LMUL1> [
>> + (match_operand:VI_QHS 3 "register_operand" " vr, vr")
>> + (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
>> + ] ANY_WREDUC)
>> + (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
>> "TARGET_VECTOR"
>> - "vwredsum<v_su>.vs\t%0,%3,%4%p1"
>> + "v<reduc_op>.vs\t%0,%3,%4%p1"
>> [(set_attr "type" "viwred")
>> (set_attr "mode" "<MODE>")])
>> ;; Float Reduction (vfred(max|min).vs)
>> -(define_insn "@pred_reduc_<reduc><mode>"
>> +(define_insn "@pred_<reduc_op><mode>"
>> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
>> (unspec:<V_LMUL1>
>> [(unspec:<VM>
>> @@ -7778,65 +7778,61 @@
>> (match_operand 7 "const_int_operand" " i, i")
>> (reg:SI VL_REGNUM)
>> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>> - (any_freduc:VF
>> - (vec_duplicate:VF
>> - (vec_select:<VEL>
>> - (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> - (parallel [(const_int 0)])))
>> - (match_operand:VF 3 "register_operand" " vr, vr"))
>> + (unspec:<V_LMUL1> [
>> + (match_operand:VF 3 "register_operand" " vr, vr")
>> + (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> + ] ANY_FREDUC)
>> (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
>> "TARGET_VECTOR"
>> - "vfred<reduc>.vs\t%0,%3,%4%p1"
>> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
>> [(set_attr "type" "vfredu")
>> (set_attr "mode" "<MODE>")])
>> -;; Float Ordered Reduction Sum (vfred[ou]sum.vs)
>> -(define_insn "@pred_reduc_plus<order><mode>"
>> +;; Float Reduction Sum (vfred[ou]sum.vs)
>> +(define_insn "@pred_<reduc_op><mode>"
>> [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
>> (unspec:<V_LMUL1>
>> - [(unspec:<V_LMUL1>
>> - [(unspec:<VM>
>> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
>> - (match_operand 5 "vector_length_operand" " rK, rK")
>> - (match_operand 6 "const_int_operand" " i, i")
>> - (match_operand 7 "const_int_operand" " i, i")
>> - (match_operand 8 "const_int_operand" " i, i")
>> - (reg:SI VL_REGNUM)
>> - (reg:SI VTYPE_REGNUM)
>> - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
>> - (plus:VF
>> - (vec_duplicate:VF
>> - (vec_select:<VEL>
>> - (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> - (parallel [(const_int 0)])))
>> - (match_operand:VF 3 "register_operand" " vr, vr"))
>> - (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
>> + [(unspec:<VM>
>> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
>> + (match_operand 5 "vector_length_operand" " rK, rK")
>> + (match_operand 6 "const_int_operand" " i, i")
>> + (match_operand 7 "const_int_operand" " i, i")
>> + (match_operand 8 "const_int_operand" " i, i")
>> + (reg:SI VL_REGNUM)
>> + (reg:SI VTYPE_REGNUM)
>> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
>> + (unspec:<V_LMUL1> [
>> + (match_operand:VF 3 "register_operand" " vr, vr")
>> + (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
>> + ] ANY_FREDUC_SUM)
>> + (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
>> "TARGET_VECTOR"
>> - "vfred<order>sum.vs\t%0,%3,%4%p1"
>> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
>> [(set_attr "type" "vfred<order>")
>> (set_attr "mode" "<MODE>")
>> (set (attr "frm_mode")
>> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>> ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
>> -(define_insn "@pred_widen_reduc_plus<order><mode>"
>> - [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
>> +(define_insn "@pred_<reduc_op><mode>"
>> + [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
>> (unspec:<V_EXT_LMUL1>
>> - [(unspec:<V_EXT_LMUL1>
>> - [(unspec:<VM>
>> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
>> - (match_operand 5 "vector_length_operand" " rK, rK")
>> - (match_operand 6 "const_int_operand" " i, i")
>> - (match_operand 7 "const_int_operand" " i, i")
>> - (match_operand 8 "const_int_operand" " i, i")
>> - (reg:SI VL_REGNUM)
>> - (reg:SI VTYPE_REGNUM)
>> - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
>> + [(unspec:<VM>
>> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
>> + (match_operand 5 "vector_length_operand" " rK, rK")
>> + (match_operand 6 "const_int_operand" " i, i")
>> + (match_operand 7 "const_int_operand" " i, i")
>> + (match_operand 8 "const_int_operand" " i, i")
>> + (reg:SI VL_REGNUM)
>> + (reg:SI VTYPE_REGNUM)
>> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
>> + (unspec:<V_EXT_LMUL1> [
>> (match_operand:VF_HS 3 "register_operand" " vr, vr")
>> (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
>> - (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
>> + ] ANY_FWREDUC_SUM)
>> + (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
>> "TARGET_VECTOR"
>> - "vfwred<order>sum.vs\t%0,%3,%4%p1"
>> + "vf<reduc_op>.vs\t%0,%3,%4%p1"
>> [(set_attr "type" "vfwred<order>")
>> (set_attr "mode" "<MODE>")
>> (set (attr "frm_mode")
>> --
>> 2.36.3
>>
>
--
Best,
Lehua
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-09-13 12:31 [PATCH 2/2] RISC-V: Refactor vector reduction patterns Lehua Ding
2023-09-14 14:10 ` 钟居哲
2023-09-14 14:53 ` Kito Cheng
2023-09-14 15:01 ` Lehua Ding
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