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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: 丁乐华 <lehua.ding@rivai.ai>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>,
	 "Robin Dapp" <rdapp.gcc@gmail.com>,
	 palmer <palmer@rivosinc.com>,
	 jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: [PATCH] RISC-V: Fix vsetvl pass ICE
Date: Thu, 31 Aug 2023 08:07:37 +0800	[thread overview]
Message-ID: <6F10CC05B8E5556B+2023083108073633385031@rivai.ai> (raw)
In-Reply-To: <20230830095134.3571077-1-lehua.ding@rivai.ai>

[-- Attachment #1: Type: text/plain, Size: 2337 bytes --]

Ok for trunk. But not sure whether it's ok for GCC-13.



juzhe.zhong@rivai.ai
 
From: Lehua Ding
Date: 2023-08-30 17:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
 
PR target/111234
 
gcc/ChangeLog:
 
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
 
---
gcc/config/riscv/riscv-vsetvl.cc              |  2 +-
.../gcc.target/riscv/rvv/vsetvl/pr111234.c    | 19 +++++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
 
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 1386d9250ca..a81bb53a521 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info &info,
     new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
   else
     {
-      if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
+      if (vsetvl_insn_p (rinsn))
new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
       else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
new file mode 100644
index 00000000000..ee5eec4a257
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include <riscv_vector.h>
+
+void
+f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
+{
+  vint32m1_t va = *in;
+  vbool32_t mask = *m;
+  vint64m2_t vb
+    = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
+  vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
+
+  if (b != 0)
+    vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 ());
+
+  *out = vc;
+}
-- 
2.36.3
 

  reply	other threads:[~2023-08-31  0:07 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-30  9:51 Lehua Ding
2023-08-31  0:07 ` juzhe.zhong [this message]
2023-08-31  1:44   ` Kito Cheng
2023-08-31  2:12     ` Lehua Ding
2023-09-18  7:54       ` Lehua Ding
2023-09-18  8:08         ` Kito Cheng
2023-09-18  8:22           ` Lehua Ding

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