Re: [PATCH V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

[Lehua Ding <lehua.ding@rivai.ai>]

Committed with splited patchs, thanks Robin.

[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631152.html

[COMMITTED V4] RISC-V: Support combine cond extend and reduce sum to 
widen reduce sum
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631153.html

On 2023/9/21 16:27, Lehua Ding wrote:
> Hi Robin,
> 
> On 2023/9/21 16:12, Robin Dapp wrote:
>> Hi Lehua,
>>
>>> V3 Change: Back to the original method.
>> Was there an original method even before the first patch?
> 
> Yes, this was the method that came to mind at first, and I didn't send a 
> patch because I didn't feel like the pattern looked good :)
> 
>> Anyway, I prefer this v3 over the others even though the large
>> pattern is not exactly pretty :)
>>
>> What about the VLS changes?  Are they necessary for the patterns/tests?
>> I mean they are reasonable in themselves but are they related?
>> If so, please specify.  If not please split them off into a small
>> (pre-approved) patch.  OK with this adjusted.
> 
> This VLS change is necessary for the patch and only used by this patch 
> currently. Currently, VLMAX inside avl_type stands for VLA mode using 
> VLMAX, however, we need to distinguish from NONVLMAX in the case where 
> the vl is the number of units of the mode. This way it is safe and 
> simple to do combine. Therefore a new avl_type enumeration VLS is 
> introduced to distinguish.
> 
> There's an overlap between VLMAX and VLS here, and it's probably more 
> appropriate to use FULL or something similar, like the other patch that 
> changes the comments. I'm going to hold off on making any major changes 
> for now, though, as the impact is more localized.
> 

-- 
Best,
Lehua (RiVAI)
lehua.ding@rivai.ai