Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

[Jeff Law <jeffreyalaw@gmail.com>]

On 3/25/24 2:57 PM, Palmer Dabbelt wrote:
> On Mon, 25 Mar 2024 13:49:18 PDT (-0700), jeffreyalaw@gmail.com wrote:
>>
>>
>> On 3/25/24 2:31 PM, Palmer Dabbelt wrote:
>>> On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote:
>>
>>>> I'd doubt it's worth the complexity.  Picking some reasonable value 
>>>> gets
>>>> you the vast majority of the benefit.   Something like
>>>> COSTS_N_INSNS(6) is enough to get CSE to trigger.  So what's left is a
>>>> reasonable cost, particularly for the division-by-constant case 
>>>> where we
>>>> need a ceiling for synth_mult.
>>>
>>> Ya, makes sense.  I noticed our multi-word multiply costs are a bit odd
>>> too (they really only work for 64-bit mul on 32-bit targets), but that's
>>> probably not worth worrying about either.
>> We do have a changes locally that adjust various costs.  One of which is
>> highpart multiply.  One of the many things to start working through once
>> gcc-15 opens for development.  Hence my desire to help keep gcc-14 on
>> track for an on-time release.
> 
> Cool.  LMK if there's anything we can do to help on that front.
I think the RISC-V space is in pretty good shape.   Most of the issues 
left are either generic or hitting other targets.  While the number of 
P1s has been flat or rising, that's more an artifact of bug 
triage/reprioritization process that's ongoing.  I can only speak for 
myself, but the progress in nailing down the slew of bugs thrown into 
the P1 bucket over the last few weeks has been great IMHO.

jeff