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Patrick On 6/24/24 12:06, Patrick O'Neill wrote: > This introduces testsuite support infra for removing extensions. > Since z* extensions don't have ordering requirements the logic for > adding/removing those extensions has also been consolidated. > > This fixes RVWMO compile testcases failing on Ztso targets by removing > the extension from the -march string. > > gcc/ChangeLog: > > * doc/sourcebuild.texi (dg-remove-option): Add documentation. > (dg-add-option): Add documentation for riscv_{a,zaamo,zalrsc,ztso} > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Add dg-remove-options > for ztso. > * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto. > * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto. > * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Replace manually > specified -march string with dg-add/remove-options directives. > * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto. > * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto. > * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto. > * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto. > * lib/target-supports-dg.exp: Add dg-remove-options. > * lib/target-supports.exp: Add dg-remove-options and consolidate z* > extension add/remove-option code. > > Signed-off-by: Patrick O'Neill > --- > Tested using rv64gcv_ztso/rv64id but relying on precommit to run the targets > there. > > Beyond testing Ztso/Zalrsc this is also helpful for the Zabha patch I'm > working on. We can continue to test the atomic subword emulation > routines without specifing a -march string. > --- > v2 ChangeLog: > Remove spare bracket that pre-commit flagged. > Add missing dg-add-options for zalrsc testcases. > --- > v3 ChangeLog: > Add documentation for dg-remove-option and document some existing riscv_* > dg-add-option options. > > Approved here: https://inbox.sourceware.org/gcc-patches/9fa5c829-1e30-444c-a091-62d05f2f22ca@gmail.com/ > I'll let it sit on the list for an hour or so before committing in case anyone > has feedback on the added docs. > --- > v4 ChangeLog: > Add missing @table to new dg-remove-option section in sourcebuild.texi as noted > by the linaro pre-commit CI. > > Approved here: https://inbox.sourceware.org/gcc-patches/9fa5c829-1e30-444c-a091-62d05f2f22ca@gmail.com/ > Will wait an hour or so before committing. > --- > gcc/doc/sourcebuild.texi | 43 ++++ > .../riscv/amo/amo-table-a-6-amo-add-1.c | 1 + > .../riscv/amo/amo-table-a-6-amo-add-2.c | 1 + > .../riscv/amo/amo-table-a-6-amo-add-3.c | 1 + > .../riscv/amo/amo-table-a-6-amo-add-4.c | 1 + > .../riscv/amo/amo-table-a-6-amo-add-5.c | 1 + > .../amo/amo-table-a-6-compare-exchange-1.c | 1 + > .../amo/amo-table-a-6-compare-exchange-2.c | 1 + > .../amo/amo-table-a-6-compare-exchange-3.c | 1 + > .../amo/amo-table-a-6-compare-exchange-4.c | 1 + > .../amo/amo-table-a-6-compare-exchange-5.c | 1 + > .../amo/amo-table-a-6-compare-exchange-6.c | 1 + > .../amo/amo-table-a-6-compare-exchange-7.c | 1 + > .../riscv/amo/amo-table-a-6-fence-1.c | 1 + > .../riscv/amo/amo-table-a-6-fence-2.c | 1 + > .../riscv/amo/amo-table-a-6-fence-3.c | 1 + > .../riscv/amo/amo-table-a-6-fence-4.c | 1 + > .../riscv/amo/amo-table-a-6-fence-5.c | 1 + > .../riscv/amo/amo-table-a-6-load-1.c | 1 + > .../riscv/amo/amo-table-a-6-load-2.c | 1 + > .../riscv/amo/amo-table-a-6-load-3.c | 1 + > .../riscv/amo/amo-table-a-6-store-1.c | 1 + > .../riscv/amo/amo-table-a-6-store-2.c | 1 + > .../riscv/amo/amo-table-a-6-store-compat-3.c | 1 + > .../amo/amo-table-a-6-subword-amo-add-1.c | 1 + > .../amo/amo-table-a-6-subword-amo-add-2.c | 1 + > .../amo/amo-table-a-6-subword-amo-add-3.c | 1 + > .../amo/amo-table-a-6-subword-amo-add-4.c | 1 + > .../amo/amo-table-a-6-subword-amo-add-5.c | 1 + > .../riscv/amo/amo-zalrsc-amo-add-1.c | 5 +- > .../riscv/amo/amo-zalrsc-amo-add-2.c | 5 +- > .../riscv/amo/amo-zalrsc-amo-add-3.c | 5 +- > .../riscv/amo/amo-zalrsc-amo-add-4.c | 5 +- > .../riscv/amo/amo-zalrsc-amo-add-5.c | 5 +- > gcc/testsuite/lib/target-supports-dg.exp | 16 ++ > gcc/testsuite/lib/target-supports.exp | 190 +++++++++++++----- > 36 files changed, 246 insertions(+), 56 deletions(-) > > diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi > index e37fb85f3b3..c6bb41d1d23 100644 > --- a/gcc/doc/sourcebuild.texi > +++ b/gcc/doc/sourcebuild.texi > @@ -1015,6 +1015,7 @@ FIXME: discuss non-C testsuites here. > * Selectors:: Selecting targets to which a test applies. > * Effective-Target Keywords:: Keywords describing target attributes. > * Add Options:: Features for @code{dg-add-options} > +* Remove Options:: Features for @code{dg-remove-options} > * Require Support:: Variants of @code{dg-require-@var{support}} > * Final Actions:: Commands for use in @code{dg-final} > @end menu > @@ -1085,6 +1086,13 @@ default, or that don't provide them at all. It must come after > all @code{dg-options} directives. > For supported values of @var{feature} see @ref{Add Options, ,}. > > +@item @{ dg-remove-options @var{feature} @dots{} @} > +Remove any compiler options that are needed to access certain features. > +This directive does nothing on targets that disable the features by > +default, or that don't provide them at all. It must come after > +all @code{dg-options} and @code{dg-add-options} directives. > +For supported values of @var{feature} see @ref{Remove Options, ,}. > + > @item @{ dg-additional-options @var{options} [@{ target @var{selector} @}] @} > This directive provides a list of compiler options, to be used > if the target system matches @var{selector}, that are added to the default > @@ -3278,6 +3286,18 @@ compliance mode. > @code{mips16} function attributes. > Only MIPS targets support this feature, and only then in certain modes. > > +@item riscv_a > +Add the 'A' extension to the -march string on RISC-V targets. > + > +@item riscv_zaamo > +Add the zaamo extension to the -march string on RISC-V targets. > + > +@item riscv_zalrsc > +Add the zalrsc extension to the -march string on RISC-V targets. > + > +@item riscv_ztso > +Add the ztso extension to the -march string on RISC-V targets. > + > @item stack_size > @anchor{stack_size_ao} > Add the flags needed to define macro STACK_SIZE and set it to the stack size > @@ -3300,6 +3320,29 @@ a target, if any. This requires the target to have an implementation of the > Add the flags needed to enable support for weak undefined symbols. > @end table > > +@node Remove Options > +@subsection Features for @code{dg-remove-options} > + > +The supported values of @var{feature} for directive @code{dg-remove-options} > +are: > + > +@table @code > +@item riscv_a > +Remove the 'A' extension and all implied extensions from the -march string on > +RISC-V targets. > + > +@item riscv_zaamo > +Remove the zaamo extension from the -march string on RISC-V. If the 'A' > +extension is present downgrade it to zalrsc. > + > +@item riscv_zalrsc > +Remove the zalrsc extension from the -march string on RISC-V. If the 'A' > +extension is present downgrade it to zaamo. > + > +@item riscv_ztso > +Remove the ztso extension from the -march string on RISC-V targets. > +@end table > + > @node Require Support > @subsection Variants of @code{dg-require-@var{support}} > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c > index 2e53abf28aa..2acad7d44bf 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c > @@ -2,6 +2,7 @@ > /* Verify that atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > /* { dg-add-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c > index 14d6b7e4b1b..ab21f079eaa 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c > @@ -2,6 +2,7 @@ > /* Verify that atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > /* { dg-add-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c > index 937a00daf4c..919ff37d096 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c > @@ -2,6 +2,7 @@ > /* Verify that atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > /* { dg-add-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c > index 7d7f4e11dd4..1531d3763b7 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c > @@ -2,6 +2,7 @@ > /* Verify that atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > /* { dg-add-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c > index e5cf1e2e9cf..03b70111a74 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c > @@ -2,6 +2,7 @@ > /* Verify that atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > /* { dg-add-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c > index 4917cd6bd2b..fd8a8bfe9c6 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c > index 121936507e3..b3cffad005d 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c > index 649c7d2b1fe..70107c40a53 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c > index 5f7fdeb1b21..faab1ab728c 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c > index f4bd7d6d842..a1435a07a21 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c > index 154764425ae..0cbc89c617c 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* Mixed mappings need to be unioned. */ > /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c > index 16712540919..957aa3c0afd 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c > index bf590489c39..202479a005e 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that fence mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c > index 9848f8cae31..7d6c73a6b50 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that fence mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c > index 3c3ce6e0d18..a53889a4fa1 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that fence mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c > index 12d71717085..63a3a234d43 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that fence mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c > index 9567b604c2c..78040bd11e9 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that fence mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c > index 948fece6125..7b99db06d75 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that load mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c > index e855db9b761..f9871b92c0b 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that load mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c > index 6e79ca72abc..35f196c23c0 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that load mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c > index ee7e7dbc8ee..eb67d1968e0 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that store mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c > index 5110512e1ad..25a998b86eb 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that store mappings match Table A.6's recommended mapping. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c > index 016e5dec87d..43880b9734a 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that store mapping are compatible with Table A.6 & A.7. */ > /* { dg-options "-O3" } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c > index 348b9c8db9c..50009f021dc 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c > index 31011580684..782ffcb0a70 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c > index 38bedcd6b41..76ec8a81d1f 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c > index d69610e2d9e..3f5fa20c87c 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c > index 976f8909bdd..7417a67f692 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c > @@ -1,6 +1,7 @@ > /* { dg-do compile } */ > /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ > /* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ > /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c > index 49c1a181d69..582e96534de 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c > @@ -1,6 +1,9 @@ > /* { dg-do compile } */ > /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ > -/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ > +/* { dg-options "-O3" } */ > +/* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c > index af93c9a182b..987429640de 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c > @@ -1,6 +1,9 @@ > /* { dg-do compile } */ > /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ > -/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ > +/* { dg-options "-O3" } */ > +/* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c > index ce68af841ea..b29966ce7d7 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c > @@ -1,6 +1,9 @@ > /* { dg-do compile } */ > /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ > -/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ > +/* { dg-options "-O3" } */ > +/* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c > index be9f847782e..5dfb7ac2bac 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c > @@ -1,6 +1,9 @@ > /* { dg-do compile } */ > /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ > -/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ > +/* { dg-options "-O3" } */ > +/* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c > index b31170c15db..fcc64131fec 100644 > --- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c > +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c > @@ -1,6 +1,9 @@ > /* { dg-do compile } */ > /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ > -/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ > +/* { dg-options "-O3" } */ > +/* { dg-add-options riscv_zalrsc } */ > +/* { dg-remove-options riscv_zaamo } */ > +/* { dg-remove-options riscv_ztso } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > /* { dg-final { check-function-bodies "**" "" } } */ > > diff --git a/gcc/testsuite/lib/target-supports-dg.exp b/gcc/testsuite/lib/target-supports-dg.exp > index 6dce9fdc1ce..a098beb368e 100644 > --- a/gcc/testsuite/lib/target-supports-dg.exp > +++ b/gcc/testsuite/lib/target-supports-dg.exp > @@ -321,6 +321,22 @@ proc dg-add-options { args } { > } > } > > +# Remove any target-specific flags needed for accessing the given list > +# of features. This must come after all dg-options. > + > +proc dg-remove-options { args } { > + upvar dg-extra-tool-flags extra-tool-flags > + > + foreach arg [lrange $args 1 end] { > + if { [info procs remove_options_for_$arg] != "" } { > + set extra-tool-flags \ > + [eval [list remove_options_for_$arg ${extra-tool-flags}]] > + } else { > + error "Unrecognized option type: $arg" > + } > + } > +} > + > # Compare flags for a test directive against flags that will be used to > # compile the test: multilib flags, flags for torture options, and either > # the default flags for this group of tests or flags specified with a > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > index ed30cd18ad6..47ef8f41fb7 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -2156,7 +2156,7 @@ proc riscv_get_arch { } { > > proc add_options_for_riscv_a { flags } { > if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > + # If there are any -march flags, we have to adjust all of them. > set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ] > return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1a ] > } > @@ -2166,9 +2166,41 @@ proc add_options_for_riscv_a { flags } { > return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]" > } > > +proc remove_options_for_riscv_a_only { flags } { > + # Only remove the 'a' extension. Useful when removing zalrsc/zaamo. > + if { [lsearch $flags -march=*] >= 0 } { > + # If there are any -march flags, we have to adjust all of them. > + set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ] > + set modified_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1 ] > + return $modified_flags > + } > + if { [check_effective_target_riscv_a] } { > + # Manually specify the -march and remove it with another call > + return [remove_options_for_riscv_a_only "$flags -march=[riscv_get_arch]"] > + } > + return $flags > +} > + > +proc remove_options_for_riscv_a { flags } { > + # Remove the 'a' extension and implied zalrsc/zaamo extensions. > + if { [lsearch $flags -march=*] >= 0 } { > + # If there are any -march flags, we have to adjust all of them. > + set modified_flags [remove_options_for_riscv_a_only $flags] > + # Also removed implied extensions > + set modified_flags [remove_options_for_riscv_z_ext zaamo $flags] > + set modified_flags [remove_options_for_riscv_z_ext zalrsc $flags] > + return $modified_flags > + } > + if { [check_effective_target_riscv_a] } { > + # Manually specify the -march and remove it with another call > + return [remove_options_for_riscv_a "$flags -march=[riscv_get_arch]"] > + } > + return $flags > +} > + > proc add_options_for_riscv_d { flags } { > if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > + # If there are any -march flags, we have to adjust all of them. > return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ] > } > if { [check_effective_target_riscv_d] } { > @@ -2177,9 +2209,21 @@ proc add_options_for_riscv_d { flags } { > return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]" > } > > +proc remove_options_for_riscv_d { flags } { > + if { [lsearch $flags -march=*] >= 0 } { > + # If there are any -march flags, we have to adjust all of them. > + return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ] > + } > + if { [check_effective_target_riscv_d] } { > + # Manually specify the -march and remove it with another call > + return [remove_options_for_riscv_d "$flags -march=[riscv_get_arch]"] > + } > + return $flags > +} > + > proc add_options_for_riscv_v { flags } { > if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > + # If there are any -march flags, we have to adjust all of them. > return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1v ] > } > if { [check_effective_target_riscv_v] } { > @@ -2188,76 +2232,120 @@ proc add_options_for_riscv_v { flags } { > return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" > } > > -proc add_options_for_riscv_zaamo { flags } { > +proc remove_options_for_riscv_v { flags } { > if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > - set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ] > - return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ] > + # If there are any -march flags, we have to adjust all of them. > + return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1 ] > } > - if { [check_effective_target_riscv_zaamo] } { > - return "$flags" > + if { [check_effective_target_riscv_v] } { > + # Manually specify the -march and remove it with another call > + return [remove_options_for_riscv_v "$flags -march=[riscv_get_arch]"] > } > - return "$flags -march=[riscv_get_arch]_zaamo" > + return $flags > } > > -proc add_options_for_riscv_zalrsc { flags } { > - if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > - set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ] > - return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ] > - } > - if { [check_effective_target_riscv_zalrsc] } { > +proc add_options_for_riscv_z_ext { ext flags } { > + if {[lsearch $flags "-march=*"] >= 0} { > + # If there are any -march flags, we have to adjust all of them. > + set modified_flags {} > + foreach flag $flags { > + if {[regexp {^-march=(\S+)} $flag match march_name]} { > + if {![string match "*_${ext}*" $march_name]} { > + set march_name "${march_name}_${ext}" > + } > + lappend modified_flags "-march=$march_name" > + } else { > + lappend modified_flags $flag > + } > + } > + return [join $modified_flags " "] > + } > + if { [check_effective_target_riscv_$ext] } { > return "$flags" > } > - return "$flags -march=[riscv_get_arch]_zalrsc" > + return "$flags -march=[riscv_get_arch]_${ext}" > } > > -proc add_options_for_riscv_zfh { flags } { > +proc remove_options_for_riscv_z_ext { ext flags } { > if { [lsearch $flags -march=*] >= 0 } { > # If there are multiple -march flags, we have to adjust all of them. > - set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zfh ] > - return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zfh[[:alnum:]_.]*)_zfh} $flags \\1 ] > + set modified_flags "" > + foreach flag $flags { > + if {[regexp {^-march=(\S+)} $flag -> march_name]} { > + # Remove "_ext" from the march_name if present > + set march_name [string map [list _${ext} {}] $march_name] > + lappend modified_flags "-march=$march_name" > + } else { > + lappend modified_flags $flag > + } > + } > + return [join $modified_flags " "] > } > - if { [check_effective_target_riscv_zfh] } { > - return "$flags" > + if { [check_effective_target_riscv_$ext] } { > + # Manually specify the -march and remove it with another call > + return [remove_options_for_riscv_z_ext $ext "$flags -march=[riscv_get_arch]"] > } > - return "$flags -march=[riscv_get_arch]_zfh" > + return $flags > } > > -proc add_options_for_riscv_ztso { flags } { > - if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > - set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_ztso ] > - return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_ztso[[:alnum:]_.]*)_ztso} $flags \\1 ] > - } > - if { [check_effective_target_riscv_ztso] } { > - return "$flags" > - } > - return "$flags -march=[riscv_get_arch]_ztso" > +proc add_options_for_riscv_zaamo { flags } { > + return [add_options_for_riscv_z_ext zaamo $flags] > } > > -proc add_options_for_riscv_zvfh { flags } { > - if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > - set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvfh ] > - return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvfh[[:alnum:]_.]*)_zvfh} $flags \\1 ] > +proc remove_options_for_riscv_zaamo { flags } { > + set modified_flags [remove_options_for_riscv_z_ext zaamo $flags] > + # If 'a' is set then zaamo will be implied. We need to downgrade instances > + # of 'a' to 'zalrsc' > + set no_a_flags [remove_options_for_riscv_a_only [split $modified_flags]] > + if {![string equal $modified_flags $no_a_flags]} { > + # 'a' was removed, add 'zalrsc' since it was previously implied > + set modified_flags [add_options_for_riscv_zalrsc [split $no_a_flags]] > } > - if { [check_effective_target_riscv_zvfh] } { > - return "$flags" > + return $modified_flags > +} > + > +proc add_options_for_riscv_zalrsc { flags } { > + return [add_options_for_riscv_z_ext zalrsc $flags] > +} > + > +proc remove_options_for_riscv_zalrsc { flags } { > + set modified_flags [remove_options_for_riscv_z_ext zalrsc $flags] > + # If 'a' is set then zalrsc will be implied. We need to downgrade instances > + # of 'a' to 'zaamo' > + set no_a_flags [remove_options_for_riscv_a_only [split $modified_flags]] > + if {![string equal $modified_flags $no_a_flags]} { > + # 'a' was removed, add 'zalrsc' since it was previously implied > + set modified_flags [add_options_for_riscv_zalrsc [split $no_a_flags]] > } > - return "$flags -march=[riscv_get_arch]_zvfh" > + return $modified_flags > +} > + > +proc add_options_for_riscv_zfh { flags } { > + return [add_options_for_riscv_z_ext zfh $flags] > +} > + > +proc remove_options_for_riscv_zfh { flags } { > + return [remove_options_for_riscv_z_ext zfh $flags] > +} > + > +proc add_options_for_riscv_ztso { flags } { > + return [add_options_for_riscv_z_ext ztso $flags] > +} > + > +proc remove_options_for_riscv_ztso { flags } { > + return [remove_options_for_riscv_z_ext ztso $flags] > +} > + > +proc remove_options_for_riscv_zvfh { flags } { > + return [add_options_for_riscv_z_ext zvfh $flags] > } > > proc add_options_for_riscv_zvbb { flags } { > - if { [lsearch $flags -march=*] >= 0 } { > - # If there are multiple -march flags, we have to adjust all of them. > - set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvbb ] > - return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvbb[[:alnum:]_.]*)_zvbb} $flags \\1 ] > - } > - if { [check_effective_target_riscv_zvbb] } { > - return "$flags" > - } > - return "$flags -march=[riscv_get_arch]_zvbb" > + return [add_options_for_riscv_z_ext zvbb $flags] > +} > + > +proc remove_options_for_riscv_zvbb { flags } { > + return [add_options_for_riscv_z_ext zvbb $flags] > } > > # Return 1 if the target OS supports running SSE executables, 0 > -- > 2.43.2 >