From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 2831A3858C60 for ; Mon, 23 Oct 2023 07:35:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2831A3858C60 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2831A3858C60 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698046519; cv=none; b=SVQLsD60G4o7JhPrYkFKkgQGtNLgNQm1afphIhmafOMJpZmI5S2r1s2pVpiIvaU7U9j7zInYzDEHvNa+UYC/GQ4eEI0rc/M8Czp/qNIDQIfHyAdBXIZ1i+IPYF3HCpXxiKerTrLEjIT1PKneYM1zel3QLrCB/UBz4KJGSr1XIK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698046519; c=relaxed/simple; bh=AItkCOp70ZkwhsoU9sut1df7lbjBNvqHfi1u1VIJ3QQ=; h=DKIM-Signature:Message-ID:Subject:From:To:Date:MIME-Version; b=Y4+p+AN6L/G9SjM0czexrivc7USpd254WhMPn8jGMqmYPeZUodRttZAofgqPq1/nBsGqkKdutR8mWWXJHf5zLw8i5N1+8fLs4CBrNTRb001FHHDLTFwA0/X2LcxrrTeUx1FZDPbcNwXqM/rU3Xfi7ABcLGUw4Q5/gWzo7No/MqE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1698046511; bh=AItkCOp70ZkwhsoU9sut1df7lbjBNvqHfi1u1VIJ3QQ=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=drTlx19eclnyb5BN4nZdZNnjpwioU4hs2yCOImlSKlovNLCel9vznVdYpsFWJUriY LlaMLlchY4Nmh0kkGsDRmxcZSX+spXfwdUBhkJdynkv6E1waROtdHPRrhcnyBX//Ed ABrxRtqMcWHmW5yR9Ln9ajhCr7N+4QNp5A0B2msc= Received: from [IPv6:240e:456:1020:63b4:a766:7e31:968e:aef5] (unknown [IPv6:240e:456:1020:63b4:a766:7e31:968e:aef5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 0551A66B4B; Mon, 23 Oct 2023 03:35:04 -0400 (EDT) Message-ID: <6d85cb0fa6fc4d2a29f7dec74f87bc8ed93943e9.camel@xry111.site> Subject: Pushed: [PATCH 0/5] LoongArch: Better balance between relaxation and scheduling From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, mengqinggang Date: Mon, 23 Oct 2023 15:34:56 +0800 In-Reply-To: <20231019140300.50323-1-xry111@xry111.site> References: <20231019140300.50323-1-xry111@xry111.site> Autocrypt: addr=xry111@xry111.site; prefer-encrypt=mutual; keydata=mDMEYnkdPhYJKwYBBAHaRw8BAQdAsY+HvJs3EVKpwIu2gN89cQT/pnrbQtlvd6Yfq7egugi0HlhpIFJ1b3lhbyA8eHJ5MTExQHhyeTExMS5zaXRlPoiTBBMWCgA7FiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQrKrSDhnnEOPHFgD8D9vUToTd1MF5bng9uPJq5y3DfpcxDp+LD3joA3U2TmwA/jZtN9xLH7CGDHeClKZK/ZYELotWfJsqRcthOIGjsdAPuDgEYnkdPhIKKwYBBAGXVQEFAQEHQG+HnNiPZseiBkzYBHwq/nN638o0NPwgYwH70wlKMZhRAwEIB4h4BBgWCgAgFiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwwACgkQrKrSDhnnEOPjXgD/euD64cxwqDIqckUaisT3VCst11RcnO5iRHm6meNIwj0BALLmWplyi7beKrOlqKfuZtCLbiAPywGfCNg8LOTt4iMD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.1 MIME-Version: 1.0 X-Spam-Status: No, score=0.1 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Pushed r14-{4848..4852}. On Thu, 2023-10-19 at 22:02 +0800, Xi Ruoyao wrote: > For relaxation we are now generating assembler macros for symbolic > addresses everywhere, but this is limiting scheduling and there are > known situations where the relaxation cannot improve the code. >=20 > 1. When we are performing LTO during a final link and the linker plugin > is used, la.global won't be relaxed because they reference to an > external or preemptable symbol. > 2. The linker currently do not relax la.tls.*. > 3. For la.local + ld/st pairs, if the address is only used once, > emitting pcalau12i + ld/st is always not worse than relying on linker > relaxation. >=20 > Add -mexplicit-relocs=3Dauto to allow the compiler to use explicit relocs > for these cases, but assembler macros for other cases.=C2=A0 Use it as th= e > default if the assembler supports both explicit relocs and relaxation. >=20 > LTO-bootstrapped and regtested on loongarch64-linux-gnu.=C2=A0 Ok for tru= nk? >=20 > Xi Ruoyao (5): > =C2=A0 LoongArch: Add enum-style -mexplicit-relocs=3D option > =C2=A0 LoongArch: Use explicit relocs for GOT access when > =C2=A0=C2=A0=C2=A0 -mexplicit-relocs=3Dauto and LTO during a final link w= ith linker > =C2=A0=C2=A0=C2=A0 plugin > =C2=A0 LoongArch: Use explicit relocs for TLS access with > =C2=A0=C2=A0=C2=A0 -mexplicit-relocs=3Dauto > =C2=A0 LoongArch: Use explicit relocs for addresses only used for one loa= d or > =C2=A0=C2=A0=C2=A0 store with -mexplicit-relocs=3Dauto and -mcmodel=3D{no= rmal,medium} > =C2=A0 LoongArch: Document -mexplicit-relocs=3D{auto,none,always} >=20 > =C2=A0.../loongarch/genopts/loongarch-strings=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 6 + > =C2=A0gcc/config/loongarch/genopts/loongarch.opt.in |=C2=A0 21 ++- > =C2=A0gcc/config/loongarch/loongarch-def.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 6 + > =C2=A0gcc/config/loongarch/loongarch-protos.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 1 + > =C2=A0gcc/config/loongarch/loongarch-str.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 5 + > =C2=A0gcc/config/loongarch/loongarch.cc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 75 ++++++++-- > =C2=A0gcc/config/loongarch/loongarch.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 3 + > =C2=A0gcc/config/loongarch/loongarch.md=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 128 +++++++++++++++++- > =C2=A0gcc/config/loongarch/loongarch.opt=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 21 ++- > =C2=A0gcc/config/loongarch/predicates.md=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 15 +- > =C2=A0gcc/doc/invoke.texi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 37 +++-- > =C2=A0.../loongarch/explicit-relocs-auto-lto.c=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0 26 ++++ > =C2=A0...-relocs-auto-single-load-store-no-anchor.c |=C2=A0=C2=A0 6 + > =C2=A0.../explicit-relocs-auto-single-load-store.c=C2=A0 |=C2=A0 14 ++ > =C2=A0.../explicit-relocs-auto-tls-ld-gd.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 9 ++ > =C2=A0.../explicit-relocs-auto-tls-le-ie.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 6 + > =C2=A016 files changed, 343 insertions(+), 36 deletions(-) > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relo= cs-auto-lto.c > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relo= cs-auto-single-load-store-no-anchor.c > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relo= cs-auto-single-load-store.c > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relo= cs-auto-tls-ld-gd.c > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relo= cs-auto-tls-le-ie.c >=20 --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University